diff --git a/include/asm-blackfin/mach-common/bits/bootrom.h b/include/asm-blackfin/mach-common/bits/bootrom.h
new file mode 100644
index 0000000..6cdaa4f
--- /dev/null
+++ b/include/asm-blackfin/mach-common/bits/bootrom.h
@@ -0,0 +1,218 @@
+/*
+ * Boot ROM Entry Points and such
+ */
+
+/* These Blackfins all have a Boot ROM that is not reusable (at all):
+ *  BF531 / BF532 / BF533
+ *  BF538 / BF539
+ *  BF561
+ * So there is nothing for us to export ;(
+ *
+ * These Blackfins started to roll with the idea that the Boot ROM can
+ * provide useful functions, but still only a few (and not really useful):
+ *  BF534 / BF536 / BF537
+ *
+ * Looking forward, Boot ROM's on newer Blackfins have quite a few
+ * nice entry points that are usable at runtime and beyond.  We'll
+ * only define known legacy parts (listed above) and otherwise just
+ * assume it's a newer part.
+ *
+ * These entry points are accomplished by placing a small jump table at
+ * the start of the Boot ROM.  This way the addresses are fixed forever.
+ */
+
+#ifndef __BFIN_PERIPHERAL_BOOTROM__
+#define __BFIN_PERIPHERAL_BOOTROM__
+
+/* All Blackfin's have the Boot ROM entry point at the same address */
+#define _BOOTROM_RESET 0xEF000000
+
+#if defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) || \
+    defined(__ADSPBF538__) || defined(__ADSPBF539__) || \
+    defined(__ADSPBF561__)
+
+	/* Nothing to export */
+
+#elif defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__)
+
+	/* The BF537 family */
+
+#define _BOOTROM_FINAL_INIT            0xEF000002
+/*       reserved                      0xEF000004 */
+#define _BOOTROM_DO_MEMORY_DMA         0xEF000006
+#define _BOOTROM_BOOT_DXE_FLASH        0xEF000008
+#define _BOOTROM_BOOT_DXE_SPI          0xEF00000A
+#define _BOOTROM_BOOT_DXE_TWI          0xEF00000C
+/*       reserved                      0xEF00000E */
+#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
+#define _BOOTROM_GET_DXE_ADDRESS_SPI   0xEF000012
+#define _BOOTROM_GET_DXE_ADDRESS_TWI   0xEF000014
+/*       reserved                      0xEF000016 */
+/*       reserved                      0xEF000018 */
+
+	/* Glue to newer Boot ROMs */
+#define _BOOTROM_MDMA                  _BOOTROM_DO_MEMORY_DMA
+#define _BOOTROM_MEMBOOT               _BOOTROM_BOOT_DXE_FLASH
+#define _BOOTROM_SPIBOOT               _BOOTROM_BOOT_DXE_FLASH
+#define _BOOTROM_TWIBOOT               _BOOTROM_BOOT_DXE_TWI
+
+#else
+
+	/* All the newer Boot ROMs */
+
+#define _BOOTROM_FINAL_INIT            0xEF000002
+#define _BOOTROM_PDMA                  0xEF000004
+#define _BOOTROM_MDMA                  0xEF000006
+#define _BOOTROM_MEMBOOT               0xEF000008
+#define _BOOTROM_SPIBOOT               0xEF00000A
+#define _BOOTROM_TWIBOOT               0xEF00000C
+/*       reserved                      0xEF00000E */
+/*       reserved                      0xEF000010 */
+/*       reserved                      0xEF000012 */
+/*       reserved                      0xEF000014 */
+/*       reserved                      0xEF000016 */
+#define _BOOTROM_OTP_COMMAND           0xEF000018
+#define _BOOTROM_OTP_READ              0xEF00001A
+#define _BOOTROM_OTP_WRITE             0xEF00001C
+#define _BOOTROM_ECC_TABLE             0xEF00001E
+#define _BOOTROM_BOOTKERNEL            0xEF000020
+#define _BOOTROM_GETPORT               0xEF000022
+#define _BOOTROM_NMI                   0xEF000024
+#define _BOOTROM_HWERROR               0xEF000026
+#define _BOOTROM_EXCEPTION             0xEF000028
+#define _BOOTROM_CRC32                 0xEF000030
+#define _BOOTROM_CRC32POLY             0xEF000032
+#define _BOOTROM_CRC32CALLBACK         0xEF000034
+#define _BOOTROM_CRC32INITCODE         0xEF000036
+#define _BOOTROM_SYSCONTROL            0xEF000038
+#define _BOOTROM_REV                   0xEF000040
+#define _BOOTROM_SESR                  0xEF001000
+
+#define BOOTROM_CAPS_ADI_BOOT_STRUCTS 1
+
+/* Not available on initial BF54x or BF52x */
+#if (defined(__ADSPBF54x__) && __SILICON_REVISION__ < 1) || \
+    (defined(__ADSPBF52x__) && __SILICON_REVISION__ < 2)
+#define BOOTROM_CAPS_SYSCONTROL 0
+#else
+#define BOOTROM_CAPS_SYSCONTROL 1
+#endif
+
+#endif
+
+#ifndef BOOTROM_CAPS_ADI_BOOT_STRUCTS
+#define BOOTROM_CAPS_ADI_BOOT_STRUCTS 0
+#endif
+#ifndef BOOTROM_CAPS_SYSCONTROL
+#define BOOTROM_CAPS_SYSCONTROL 0
+#endif
+
+#ifndef __ASSEMBLY__
+
+/* Structures for the syscontrol() function */
+typedef struct ADI_SYSCTRL_VALUES {
+	uint16_t uwVrCtl;
+	uint16_t uwPllCtl;
+	uint16_t uwPllDiv;
+	uint16_t uwPllLockCnt;
+	uint16_t uwPllStat;
+} ADI_SYSCTRL_VALUES;
+
+#ifndef _BOOTROM_SYSCONTROL
+#define _BOOTROM_SYSCONTROL 0
+#endif
+static uint32_t (* const syscontrol)(uint32_t action_flags, ADI_SYSCTRL_VALUES *power_settings, void *reserved) = (void *)_BOOTROM_SYSCONTROL;
+
+#endif /* __ASSEMBLY__ */
+
+/* Possible syscontrol action flags */
+#define SYSCTRL_READ        0x00000000    /* read registers */
+#define SYSCTRL_WRITE       0x00000001    /* write registers */
+#define SYSCTRL_SYSRESET    0x00000002    /* perform system reset */
+#define SYSCTRL_SOFTRESET   0x00000004    /* perform core and system reset */
+#define SYSCTRL_VRCTL       0x00000010    /* read/write VR_CTL register */
+#define SYSCTRL_EXTVOLTAGE  0x00000020    /* VDDINT supplied externally */
+#define SYSCTRL_INTVOLTAGE  0x00000000    /* VDDINT generated by on-chip regulator */
+#define SYSCTRL_OTPVOLTAGE  0x00000040    /* For Factory Purposes Only */
+#define SYSCTRL_PLLCTL      0x00000100    /* read/write PLL_CTL register */
+#define SYSCTRL_PLLDIV      0x00000200    /* read/write PLL_DIV register */
+#define SYSCTRL_LOCKCNT     0x00000400    /* read/write PLL_LOCKCNT register */
+#define SYSCTRL_PLLSTAT     0x00000800    /* read/write PLL_STAT register */
+
+#ifndef __ASSEMBLY__
+
+/* Structures for working with LDRs and boot rom callbacks */
+typedef struct ADI_BOOT_HEADER {
+	int32_t dBlockCode;
+	void    *pTargetAddress;
+	int32_t dByteCount;
+	int32_t dArgument;
+} ADI_BOOT_HEADER;
+
+typedef struct ADI_BOOT_BUFFER {
+	void    *pSource;
+	int32_t dByteCount;
+} ADI_BOOT_BUFFER;
+
+typedef struct ADI_BOOT_DATA {
+	void    *pSource;
+	void    *pDestination;
+	int16_t *pControlRegister;
+	int16_t *pDmaControlRegister;
+	int32_t dControlValue;
+	int32_t dByteCount;
+	int32_t dFlags;
+	int16_t uwDataWidth;
+	int16_t uwSrcModifyMult;
+	int16_t uwDstModifyMult;
+	int16_t uwHwait;
+	int16_t uwSsel;
+	int16_t uwUserShort;
+	int32_t dUserLong;
+	int32_t dReserved2;
+	void    *pErrorFunction;
+	void    *pLoadFunction;
+	void    *pCallBackFunction;
+	ADI_BOOT_HEADER *pHeader;
+	void    *pTempBuffer;
+	void    *pTempCurrent;
+	int32_t dTempByteCount;
+	int32_t dBlockCount;
+	int32_t dClock;
+	void    *pLogBuffer;
+	void    *pLogCurrent;
+	int32_t dLogByteCount;
+} ADI_BOOT_DATA;
+
+#endif /* __ASSEMBLY__ */
+
+/* Bit defines for ADI_BOOT_DATA->dFlags */
+#define BFLAG_DMACODE_MASK 0x0000000F
+#define BFLAG_SAFE         0x00000010
+#define BFLAG_AUX          0x00000020
+#define BFLAG_FILL         0x00000100
+#define BFLAG_QUICKBOOT    0x00000200
+#define BFLAG_CALLBACK     0x00000400
+#define BFLAG_INIT         0x00000800
+#define BFLAG_IGNORE       0x00001000
+#define BFLAG_INDIRECT     0x00002000
+#define BFLAG_FIRST        0x00004000
+#define BFLAG_FINAL        0x00008000
+#define BFLAG_HOOK         0x00400000
+#define BFLAG_HDRINDIRECT  0x00800000
+#define BFLAG_TYPE_MASK    0x00300000
+#define BFLAG_TYPE_1       0x00000000
+#define BFLAG_TYPE_2       0x00100000
+#define BFLAG_TYPE_3       0x00200000
+#define BFLAG_TYPE_4       0x00300000
+#define BFLAG_FASTREAD     0x00400000
+#define BFLAG_NOAUTO       0x01000000
+#define BFLAG_PERIPHERAL   0x02000000
+#define BFLAG_SLAVE        0x04000000
+#define BFLAG_WAKEUP       0x08000000
+#define BFLAG_NEXTDXE      0x10000000
+#define BFLAG_RETURN       0x20000000
+#define BFLAG_RESET        0x40000000
+#define BFLAG_NONRESTORE   0x80000000
+
+#endif
diff --git a/include/asm-blackfin/mach-common/bits/core.h b/include/asm-blackfin/mach-common/bits/core.h
new file mode 100644
index 0000000..d8cee10
--- /dev/null
+++ b/include/asm-blackfin/mach-common/bits/core.h
@@ -0,0 +1,109 @@
+/*
+ * Misc Core Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_CORE__
+#define __BFIN_PERIPHERAL_CORE__
+
+/*
+ * EVT registers (ILAT, IMASK, and IPEND).
+ */
+
+#define EVT_EMU_P		0	/* Emulator interrupt bit position */
+#define EVT_RST_P		1	/* Reset interrupt bit position */
+#define EVT_NMI_P		2	/* Non Maskable interrupt bit position */
+#define EVT_EVX_P		3	/* Exception bit position */
+#define EVT_IRPTEN_P		4	/* Global interrupt enable bit position */
+#define EVT_IVHW_P		5	/* Hardware Error interrupt bit position */
+#define EVT_IVTMR_P		6	/* Timer interrupt bit position */
+#define EVT_IVG7_P		7	/* IVG7 interrupt bit position */
+#define EVT_IVG8_P		8	/* IVG8 interrupt bit position */
+#define EVT_IVG9_P		9	/* IVG9 interrupt bit position */
+#define EVT_IVG10_P		10	/* IVG10 interrupt bit position */
+#define EVT_IVG11_P		11	/* IVG11 interrupt bit position */
+#define EVT_IVG12_P		12	/* IVG12 interrupt bit position */
+#define EVT_IVG13_P		13	/* IVG13 interrupt bit position */
+#define EVT_IVG14_P		14	/* IVG14 interrupt bit position */
+#define EVT_IVG15_P		15	/* IVG15 interrupt bit position */
+
+#define EVT_EMU			MK_BMSK_(EVT_EMU_P   )	/* Emulator interrupt mask */
+#define EVT_RST			MK_BMSK_(EVT_RST_P   )	/* Reset interrupt mask */
+#define EVT_NMI			MK_BMSK_(EVT_NMI_P   )	/* Non Maskable interrupt mask */
+#define EVT_EVX			MK_BMSK_(EVT_EVX_P   )	/* Exception mask */
+#define EVT_IRPTEN		MK_BMSK_(EVT_IRPTEN_P)	/* Global interrupt enable mask */
+#define EVT_IVHW		MK_BMSK_(EVT_IVHW_P  )	/* Hardware Error interrupt mask */
+#define EVT_IVTMR		MK_BMSK_(EVT_IVTMR_P )	/* Timer interrupt mask */
+#define EVT_IVG7		MK_BMSK_(EVT_IVG7_P  )	/* IVG7 interrupt mask */
+#define EVT_IVG8		MK_BMSK_(EVT_IVG8_P  )	/* IVG8 interrupt mask */
+#define EVT_IVG9		MK_BMSK_(EVT_IVG9_P  )	/* IVG9 interrupt mask */
+#define EVT_IVG10		MK_BMSK_(EVT_IVG10_P )	/* IVG10 interrupt mask */
+#define EVT_IVG11		MK_BMSK_(EVT_IVG11_P )	/* IVG11 interrupt mask */
+#define EVT_IVG12		MK_BMSK_(EVT_IVG12_P )	/* IVG12 interrupt mask */
+#define EVT_IVG13		MK_BMSK_(EVT_IVG13_P )	/* IVG13 interrupt mask */
+#define EVT_IVG14		MK_BMSK_(EVT_IVG14_P )	/* IVG14 interrupt mask */
+#define EVT_IVG15		MK_BMSK_(EVT_IVG15_P )	/* IVG15 interrupt mask */
+
+/*
+ * SEQSTAT register
+ */
+
+#define EXCAUSE_P	0	/* Last exception cause bit positions */
+#define EXCAUSE0_P	0	/* Last exception cause bit 0 */
+#define EXCAUSE1_P	1	/* Last exception cause bit 1 */
+#define EXCAUSE2_P	2	/* Last exception cause bit 2 */
+#define EXCAUSE3_P	3	/* Last exception cause bit 3 */
+#define EXCAUSE4_P	4	/* Last exception cause bit 4 */
+#define EXCAUSE5_P	5	/* Last exception cause bit 5 */
+#define IDLE_REQ_P	12	/* Pending idle mode request, set by IDLE instruction */
+#define SFTRESET_P	13	/* Indicates whether the last reset was a software reset (=1) */
+#define HWERRCAUSE_P	14	/* Last hw error cause bit positions */
+#define HWERRCAUSE0_P	14	/* Last hw error cause bit 0 */
+#define HWERRCAUSE1_P	15	/* Last hw error cause bit 1 */
+#define HWERRCAUSE2_P	16	/* Last hw error cause bit 2 */
+#define HWERRCAUSE3_P	17	/* Last hw error cause bit 3 */
+#define HWERRCAUSE4_P	18	/* Last hw error cause bit 4 */
+#define HWERRCAUSE5_P	19	/* Last hw error cause bit 5 */
+#define HWERRCAUSE6_P	20	/* Last hw error cause bit 6 */
+#define HWERRCAUSE7_P	21	/* Last hw error cause bit 7 */
+
+#define EXCAUSE \
+	( MK_BMSK_(EXCAUSE0_P) | \
+	  MK_BMSK_(EXCAUSE1_P) | \
+	  MK_BMSK_(EXCAUSE2_P) | \
+	  MK_BMSK_(EXCAUSE3_P) | \
+	  MK_BMSK_(EXCAUSE4_P) | \
+	  MK_BMSK_(EXCAUSE5_P) )
+#define SFTRESET \
+	( MK_BMSK_(SFTRESET_P) )
+#define HWERRCAUSE \
+	( MK_BMSK_(HWERRCAUSE0_P) | \
+	  MK_BMSK_(HWERRCAUSE1_P) | \
+	  MK_BMSK_(HWERRCAUSE2_P) | \
+	  MK_BMSK_(HWERRCAUSE3_P) | \
+	  MK_BMSK_(HWERRCAUSE4_P) )
+
+/* SWRST Masks */
+#define SYSTEM_RESET		0x0007		/* Initiates A System Software Reset */
+#ifdef __ADSPBF561__
+# define DOUBLE_FAULT_A		0x0008
+# define DOUBLE_FAULT_B		0x0010
+# define DOUBLE_FAULT		0x0018		/* Core [A|B] Double Fault Causes Reset */
+# define RESET_DOUBLE_A		0x0800
+# define RESET_DOUBLE_B		0x1000
+# define RESET_DOUBLE		0x1800		/* SW Reset Generated By Core [A|B] Double-Fault */
+# define RESET_WDOG_B		0x2000
+# define RESET_WDOG_A		0x4000
+# define RESET_WDOG		0x6000		/* SW Reset Generated By Watchdog [A|B] Timer */
+#else
+# define DOUBLE_FAULT		0x0008		/* Core Double Fault Causes Reset */
+# define RESET_DOUBLE		0x2000		/* SW Reset Generated By Core Double-Fault */
+# define RESET_WDOG		0x4000		/* SW Reset Generated By Watchdog Timer */
+#endif
+#define RESET_SOFTWARE		0x8000		/* SW Reset Occurred Since Last Read Of SWRST */
+
+/* SYSCFG Masks */
+#define SSSTEP			0x00000001	/* Supervisor Single Step */
+#define CCEN			0x00000002	/* Cycle Counter Enable */
+#define SNEN			0x00000004	/* Self-Nesting Interrupt Enable */
+
+#endif
diff --git a/include/asm-blackfin/mach-common/bits/dma.h b/include/asm-blackfin/mach-common/bits/dma.h
new file mode 100644
index 0000000..136313e
--- /dev/null
+++ b/include/asm-blackfin/mach-common/bits/dma.h
@@ -0,0 +1,58 @@
+/*
+ * DMA Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_DMA__
+#define __BFIN_PERIPHERAL_DMA__
+
+/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
+#define DMAEN			0x0001	/* DMA Channel Enable */
+#define WNR			0x0002	/* Channel Direction (W/R*) */
+#define WDSIZE_8		0x0000	/* Transfer Word Size = 8 */
+#define WDSIZE_16		0x0004	/* Transfer Word Size = 16 */
+#define WDSIZE_32		0x0008	/* Transfer Word Size = 32 */
+#define DMA2D			0x0010	/* DMA Mode (2D/1D*) */
+#define RESTART			0x0020	/* DMA Buffer Clear */
+#define DI_SEL			0x0040	/* Data Interrupt Timing Select */
+#define DI_EN			0x0080	/* Data Interrupt Enable */
+#define NDSIZE			0x0F00	/* Next Descriptor bitmask */
+#define NDSIZE_0		0x0000	/* Next Descriptor Size = 0 (Stop/Autobuffer) */
+#define NDSIZE_1		0x0100	/* Next Descriptor Size = 1 */
+#define NDSIZE_2		0x0200	/* Next Descriptor Size = 2 */
+#define NDSIZE_3		0x0300	/* Next Descriptor Size = 3 */
+#define NDSIZE_4		0x0400	/* Next Descriptor Size = 4 */
+#define NDSIZE_5		0x0500	/* Next Descriptor Size = 5 */
+#define NDSIZE_6		0x0600	/* Next Descriptor Size = 6 */
+#define NDSIZE_7		0x0700	/* Next Descriptor Size = 7 */
+#define NDSIZE_8		0x0800	/* Next Descriptor Size = 8 */
+#define NDSIZE_9		0x0900	/* Next Descriptor Size = 9 */
+#define FLOW_STOP		0x0000	/* Stop Mode */
+#define FLOW_AUTO		0x1000	/* Autobuffer Mode */
+#define FLOW_ARRAY		0x4000	/* Descriptor Array Mode */
+#define FLOW_SMALL		0x6000	/* Small Model Descriptor List Mode */
+#define FLOW_LARGE		0x7000	/* Large Model Descriptor List Mode */
+
+#define DMAEN_P			0	/* Channel Enable */
+#define WNR_P			1	/* Channel Direction (W/R*) */
+#define DMA2D_P			4	/* 2D/1D* Mode */
+#define RESTART_P		5	/* Restart */
+#define DI_SEL_P		6	/* Data Interrupt Select */
+#define DI_EN_P			7	/* Data Interrupt Enable */
+
+/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
+#define DMA_DONE		0x0001	/* DMA Completion Interrupt Status */
+#define DMA_ERR			0x0002	/* DMA Error Interrupt Status */
+#define DFETCH			0x0004	/* DMA Descriptor Fetch Indicator */
+#define DMA_RUN			0x0008	/* DMA Channel Running Indicator */
+
+#define DMA_DONE_P		0	/* DMA Done Indicator */
+#define DMA_ERR_P		1	/* DMA Error Indicator */
+#define DFETCH_P		2	/* Descriptor Fetch Indicator */
+#define DMA_RUN_P		3	/* DMA Running Indicator */
+
+/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
+#define CTYPE			0x0040	/* DMA Channel Type Indicator (Memory/Peripheral*) */
+#define CTYPE_P			6	/* DMA Channel Type Indicator BIT POSITION */
+#define PMAP			0xF000	/* Peripheral Mapped To This Channel */
+
+#endif
diff --git a/include/asm-blackfin/mach-common/bits/ebiu.h b/include/asm-blackfin/mach-common/bits/ebiu.h
new file mode 100644
index 0000000..ab530ad
--- /dev/null
+++ b/include/asm-blackfin/mach-common/bits/ebiu.h
@@ -0,0 +1,421 @@
+/*
+ * EBIU Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_EBIU__
+#define __BFIN_PERIPHERAL_EBIU__
+
+/* EBIU_AMGCTL Masks */
+#define AMCKEN		0x0001		/* Enable CLKOUT */
+#define AMBEN_NONE	0x0000		/* All Banks Disabled */
+#define AMBEN_B0	0x0002		/* Enable Asynchronous Memory Bank 0 only */
+#define AMBEN_B0_B1	0x0004		/* Enable Asynchronous Memory Banks 0 & 1 only */
+#define AMBEN_B0_B1_B2	0x0006		/* Enable Asynchronous Memory Banks 0,/ 1, and 2 */
+#define AMBEN_ALL	0x0008		/* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
+#define B0_PEN		0x0010		/* Enable 16-bit packing Bank 0 */
+#define B1_PEN		0x0020		/* Enable 16-bit packing Bank 1 */
+#define B2_PEN		0x0040		/* Enable 16-bit packing Bank 2 */
+#define B3_PEN		0x0080		/* Enable 16-bit packing Bank 3 */
+#define CDPRIO		0x0100		/* Core has priority over DMA for external accesses */
+
+/* EBIU_AMGCTL Bit Positions */
+#define AMCKEN_P	0x00000000	/* Enable CLKOUT */
+#define AMBEN_P0	0x00000001	/* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
+#define AMBEN_P1	0x00000002	/* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */
+#define AMBEN_P2	0x00000003	/* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
+#define B0_PEN_P	0x00000004	/* Enable 16-bit packing Bank 0 */
+#define B1_PEN_P	0x00000005	/* Enable 16-bit packing Bank 1 */
+#define B2_PEN_P	0x00000006	/* Enable 16-bit packing Bank 2 */
+#define B3_PEN_P	0x00000007	/* Enable 16-bit packing Bank 3 */
+#define CDPRIO_P	0x00000008	/* Core has priority over DMA for external accesses */
+
+/* EBIU_AMBCTL0 Masks */
+#define B0RDYEN		0x00000001	/* Bank 0 RDY Enable, 0=disable, 1=enable */
+#define B0RDYPOL	0x00000002	/* Bank 0 RDY Active high, 0=active low, 1=active high */
+#define B0TT_1		0x00000004	/* Bank 0 Transition Time from Read to Write = 1 cycle */
+#define B0TT_2		0x00000008	/* Bank 0 Transition Time from Read to Write = 2 cycles */
+#define B0TT_3		0x0000000C	/* Bank 0 Transition Time from Read to Write = 3 cycles */
+#define B0TT_4		0x00000000	/* Bank 0 Transition Time from Read to Write = 4 cycles */
+#define B0ST_1		0x00000010	/* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
+#define B0ST_2		0x00000020	/* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
+#define B0ST_3		0x00000030	/* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
+#define B0ST_4		0x00000000	/* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
+#define B0HT_1		0x00000040	/* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
+#define B0HT_2		0x00000080	/* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
+#define B0HT_3		0x000000C0	/* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
+#define B0HT_0		0x00000000	/* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
+#define B0RAT_1		0x00000100	/* Bank 0 Read Access Time = 1 cycle */
+#define B0RAT_2		0x00000200	/* Bank 0 Read Access Time = 2 cycles */
+#define B0RAT_3		0x00000300	/* Bank 0 Read Access Time = 3 cycles */
+#define B0RAT_4		0x00000400	/* Bank 0 Read Access Time = 4 cycles */
+#define B0RAT_5		0x00000500	/* Bank 0 Read Access Time = 5 cycles */
+#define B0RAT_6		0x00000600	/* Bank 0 Read Access Time = 6 cycles */
+#define B0RAT_7		0x00000700	/* Bank 0 Read Access Time = 7 cycles */
+#define B0RAT_8		0x00000800	/* Bank 0 Read Access Time = 8 cycles */
+#define B0RAT_9		0x00000900	/* Bank 0 Read Access Time = 9 cycles */
+#define B0RAT_10	0x00000A00	/* Bank 0 Read Access Time = 10 cycles */
+#define B0RAT_11	0x00000B00	/* Bank 0 Read Access Time = 11 cycles */
+#define B0RAT_12	0x00000C00	/* Bank 0 Read Access Time = 12 cycles */
+#define B0RAT_13	0x00000D00	/* Bank 0 Read Access Time = 13 cycles */
+#define B0RAT_14	0x00000E00	/* Bank 0 Read Access Time = 14 cycles */
+#define B0RAT_15	0x00000F00	/* Bank 0 Read Access Time = 15 cycles */
+#define B0WAT_1		0x00001000	/* Bank 0 Write Access Time = 1 cycle */
+#define B0WAT_2		0x00002000	/* Bank 0 Write Access Time = 2 cycles */
+#define B0WAT_3		0x00003000	/* Bank 0 Write Access Time = 3 cycles */
+#define B0WAT_4		0x00004000	/* Bank 0 Write Access Time = 4 cycles */
+#define B0WAT_5		0x00005000	/* Bank 0 Write Access Time = 5 cycles */
+#define B0WAT_6		0x00006000	/* Bank 0 Write Access Time = 6 cycles */
+#define B0WAT_7		0x00007000	/* Bank 0 Write Access Time = 7 cycles */
+#define B0WAT_8		0x00008000	/* Bank 0 Write Access Time = 8 cycles */
+#define B0WAT_9		0x00009000	/* Bank 0 Write Access Time = 9 cycles */
+#define B0WAT_10	0x0000A000	/* Bank 0 Write Access Time = 10 cycles */
+#define B0WAT_11	0x0000B000	/* Bank 0 Write Access Time = 11 cycles */
+#define B0WAT_12	0x0000C000	/* Bank 0 Write Access Time = 12 cycles */
+#define B0WAT_13	0x0000D000	/* Bank 0 Write Access Time = 13 cycles */
+#define B0WAT_14	0x0000E000	/* Bank 0 Write Access Time = 14 cycles */
+#define B0WAT_15	0x0000F000	/* Bank 0 Write Access Time = 15 cycles */
+#define B1RDYEN		0x00010000	/* Bank 1 RDY enable, 0=disable, 1=enable */
+#define B1RDYPOL	0x00020000	/* Bank 1 RDY Active high, 0=active low, 1=active high */
+#define B1TT_1		0x00040000	/* Bank 1 Transition Time from Read to Write = 1 cycle */
+#define B1TT_2		0x00080000	/* Bank 1 Transition Time from Read to Write = 2 cycles */
+#define B1TT_3		0x000C0000	/* Bank 1 Transition Time from Read to Write = 3 cycles */
+#define B1TT_4		0x00000000	/* Bank 1 Transition Time from Read to Write = 4 cycles */
+#define B1ST_1		0x00100000	/* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B1ST_2		0x00200000	/* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B1ST_3		0x00300000	/* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B1ST_4		0x00000000	/* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B1HT_1		0x00400000	/* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B1HT_2		0x00800000	/* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B1HT_3		0x00C00000	/* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B1HT_0		0x00000000	/* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
+#define B1RAT_1		0x01000000	/* Bank 1 Read Access Time = 1 cycle */
+#define B1RAT_2		0x02000000	/* Bank 1 Read Access Time = 2 cycles */
+#define B1RAT_3		0x03000000	/* Bank 1 Read Access Time = 3 cycles */
+#define B1RAT_4		0x04000000	/* Bank 1 Read Access Time = 4 cycles */
+#define B1RAT_5		0x05000000	/* Bank 1 Read Access Time = 5 cycles */
+#define B1RAT_6		0x06000000	/* Bank 1 Read Access Time = 6 cycles */
+#define B1RAT_7		0x07000000	/* Bank 1 Read Access Time = 7 cycles */
+#define B1RAT_8		0x08000000	/* Bank 1 Read Access Time = 8 cycles */
+#define B1RAT_9		0x09000000	/* Bank 1 Read Access Time = 9 cycles */
+#define B1RAT_10	0x0A000000	/* Bank 1 Read Access Time = 10 cycles */
+#define B1RAT_11	0x0B000000	/* Bank 1 Read Access Time = 11 cycles */
+#define B1RAT_12	0x0C000000	/* Bank 1 Read Access Time = 12 cycles */
+#define B1RAT_13	0x0D000000	/* Bank 1 Read Access Time = 13 cycles */
+#define B1RAT_14	0x0E000000	/* Bank 1 Read Access Time = 14 cycles */
+#define B1RAT_15	0x0F000000	/* Bank 1 Read Access Time = 15 cycles */
+#define B1WAT_1		0x10000000	/* Bank 1 Write Access Time = 1 cycle */
+#define B1WAT_2		0x20000000	/* Bank 1 Write Access Time = 2 cycles */
+#define B1WAT_3		0x30000000	/* Bank 1 Write Access Time = 3 cycles */
+#define B1WAT_4		0x40000000	/* Bank 1 Write Access Time = 4 cycles */
+#define B1WAT_5		0x50000000	/* Bank 1 Write Access Time = 5 cycles */
+#define B1WAT_6		0x60000000	/* Bank 1 Write Access Time = 6 cycles */
+#define B1WAT_7		0x70000000	/* Bank 1 Write Access Time = 7 cycles */
+#define B1WAT_8		0x80000000	/* Bank 1 Write Access Time = 8 cycles */
+#define B1WAT_9		0x90000000	/* Bank 1 Write Access Time = 9 cycles */
+#define B1WAT_10	0xA0000000	/* Bank 1 Write Access Time = 10 cycles */
+#define B1WAT_11	0xB0000000	/* Bank 1 Write Access Time = 11 cycles */
+#define B1WAT_12	0xC0000000	/* Bank 1 Write Access Time = 12 cycles */
+#define B1WAT_13	0xD0000000	/* Bank 1 Write Access Time = 13 cycles */
+#define B1WAT_14	0xE0000000	/* Bank 1 Write Access Time = 14 cycles */
+#define B1WAT_15	0xF0000000	/* Bank 1 Write Access Time = 15 cycles */
+
+/* EBIU_AMBCTL1 Masks */
+#define B2RDYEN		0x00000001	/* Bank 2 RDY Enable, 0=disable, 1=enable */
+#define B2RDYPOL	0x00000002	/* Bank 2 RDY Active high, 0=active low, 1=active high */
+#define B2TT_1		0x00000004	/* Bank 2 Transition Time from Read to Write = 1 cycle */
+#define B2TT_2		0x00000008	/* Bank 2 Transition Time from Read to Write = 2 cycles */
+#define B2TT_3		0x0000000C	/* Bank 2 Transition Time from Read to Write = 3 cycles */
+#define B2TT_4		0x00000000	/* Bank 2 Transition Time from Read to Write = 4 cycles */
+#define B2ST_1		0x00000010	/* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B2ST_2		0x00000020	/* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B2ST_3		0x00000030	/* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B2ST_4		0x00000000	/* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B2HT_1		0x00000040	/* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B2HT_2		0x00000080	/* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B2HT_3		0x000000C0	/* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B2HT_0		0x00000000	/* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
+#define B2RAT_1		0x00000100	/* Bank 2 Read Access Time = 1 cycle */
+#define B2RAT_2		0x00000200	/* Bank 2 Read Access Time = 2 cycles */
+#define B2RAT_3		0x00000300	/* Bank 2 Read Access Time = 3 cycles */
+#define B2RAT_4		0x00000400	/* Bank 2 Read Access Time = 4 cycles */
+#define B2RAT_5		0x00000500	/* Bank 2 Read Access Time = 5 cycles */
+#define B2RAT_6		0x00000600	/* Bank 2 Read Access Time = 6 cycles */
+#define B2RAT_7		0x00000700	/* Bank 2 Read Access Time = 7 cycles */
+#define B2RAT_8		0x00000800	/* Bank 2 Read Access Time = 8 cycles */
+#define B2RAT_9		0x00000900	/* Bank 2 Read Access Time = 9 cycles */
+#define B2RAT_10	0x00000A00	/* Bank 2 Read Access Time = 10 cycles */
+#define B2RAT_11	0x00000B00	/* Bank 2 Read Access Time = 11 cycles */
+#define B2RAT_12	0x00000C00	/* Bank 2 Read Access Time = 12 cycles */
+#define B2RAT_13	0x00000D00	/* Bank 2 Read Access Time = 13 cycles */
+#define B2RAT_14	0x00000E00	/* Bank 2 Read Access Time = 14 cycles */
+#define B2RAT_15	0x00000F00	/* Bank 2 Read Access Time = 15 cycles */
+#define B2WAT_1		0x00001000	/* Bank 2 Write Access Time = 1 cycle */
+#define B2WAT_2		0x00002000	/* Bank 2 Write Access Time = 2 cycles */
+#define B2WAT_3		0x00003000	/* Bank 2 Write Access Time = 3 cycles */
+#define B2WAT_4		0x00004000	/* Bank 2 Write Access Time = 4 cycles */
+#define B2WAT_5		0x00005000	/* Bank 2 Write Access Time = 5 cycles */
+#define B2WAT_6		0x00006000	/* Bank 2 Write Access Time = 6 cycles */
+#define B2WAT_7		0x00007000	/* Bank 2 Write Access Time = 7 cycles */
+#define B2WAT_8		0x00008000	/* Bank 2 Write Access Time = 8 cycles */
+#define B2WAT_9		0x00009000	/* Bank 2 Write Access Time = 9 cycles */
+#define B2WAT_10	0x0000A000	/* Bank 2 Write Access Time = 10 cycles */
+#define B2WAT_11	0x0000B000	/* Bank 2 Write Access Time = 11 cycles */
+#define B2WAT_12	0x0000C000	/* Bank 2 Write Access Time = 12 cycles */
+#define B2WAT_13	0x0000D000	/* Bank 2 Write Access Time = 13 cycles */
+#define B2WAT_14	0x0000E000	/* Bank 2 Write Access Time = 14 cycles */
+#define B2WAT_15	0x0000F000	/* Bank 2 Write Access Time = 15 cycles */
+#define B3RDYEN		0x00010000	/* Bank 3 RDY enable, 0=disable, 1=enable */
+#define B3RDYPOL	0x00020000	/* Bank 3 RDY Active high, 0=active low, 1=active high */
+#define B3TT_1		0x00040000	/* Bank 3 Transition Time from Read to Write = 1 cycle */
+#define B3TT_2		0x00080000	/* Bank 3 Transition Time from Read to Write = 2 cycles */
+#define B3TT_3		0x000C0000	/* Bank 3 Transition Time from Read to Write = 3 cycles */
+#define B3TT_4		0x00000000	/* Bank 3 Transition Time from Read to Write = 4 cycles */
+#define B3ST_1		0x00100000	/* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B3ST_2		0x00200000	/* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B3ST_3		0x00300000	/* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B3ST_4		0x00000000	/* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B3HT_1		0x00400000	/* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B3HT_2		0x00800000	/* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B3HT_3		0x00C00000	/* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B3HT_0		0x00000000	/* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
+#define B3RAT_1		0x01000000	/* Bank 3 Read Access Time = 1 cycle */
+#define B3RAT_2		0x02000000	/* Bank 3 Read Access Time = 2 cycles */
+#define B3RAT_3		0x03000000	/* Bank 3 Read Access Time = 3 cycles */
+#define B3RAT_4		0x04000000	/* Bank 3 Read Access Time = 4 cycles */
+#define B3RAT_5		0x05000000	/* Bank 3 Read Access Time = 5 cycles */
+#define B3RAT_6		0x06000000	/* Bank 3 Read Access Time = 6 cycles */
+#define B3RAT_7		0x07000000	/* Bank 3 Read Access Time = 7 cycles */
+#define B3RAT_8		0x08000000	/* Bank 3 Read Access Time = 8 cycles */
+#define B3RAT_9		0x09000000	/* Bank 3 Read Access Time = 9 cycles */
+#define B3RAT_10	0x0A000000	/* Bank 3 Read Access Time = 10 cycles */
+#define B3RAT_11	0x0B000000	/* Bank 3 Read Access Time = 11 cycles */
+#define B3RAT_12	0x0C000000	/* Bank 3 Read Access Time = 12 cycles */
+#define B3RAT_13	0x0D000000	/* Bank 3 Read Access Time = 13 cycles */
+#define B3RAT_14	0x0E000000	/* Bank 3 Read Access Time = 14 cycles */
+#define B3RAT_15	0x0F000000	/* Bank 3 Read Access Time = 15 cycles */
+#define B3WAT_1		0x10000000	/* Bank 3 Write Access Time = 1 cycle */
+#define B3WAT_2		0x20000000	/* Bank 3 Write Access Time = 2 cycles */
+#define B3WAT_3		0x30000000	/* Bank 3 Write Access Time = 3 cycles */
+#define B3WAT_4		0x40000000	/* Bank 3 Write Access Time = 4 cycles */
+#define B3WAT_5		0x50000000	/* Bank 3 Write Access Time = 5 cycles */
+#define B3WAT_6		0x60000000	/* Bank 3 Write Access Time = 6 cycles */
+#define B3WAT_7		0x70000000	/* Bank 3 Write Access Time = 7 cycles */
+#define B3WAT_8		0x80000000	/* Bank 3 Write Access Time = 8 cycles */
+#define B3WAT_9		0x90000000	/* Bank 3 Write Access Time = 9 cycles */
+#define B3WAT_10	0xA0000000	/* Bank 3 Write Access Time = 10 cycles */
+#define B3WAT_11	0xB0000000	/* Bank 3 Write Access Time = 11 cycles */
+#define B3WAT_12	0xC0000000	/* Bank 3 Write Access Time = 12 cycles */
+#define B3WAT_13	0xD0000000	/* Bank 3 Write Access Time = 13 cycles */
+#define B3WAT_14	0xE0000000	/* Bank 3 Write Access Time = 14 cycles */
+#define B3WAT_15	0xF0000000	/* Bank 3 Write Access Time = 15 cycles */
+
+/* Only available on newer parts */
+#ifdef EBIU_MODE
+
+/* EBIU_MBSCTL Bit Positions */
+#define AMSB0CTL_P	0
+#define AMSB1CTL_P	2
+#define AMSB2CTL_P	4
+#define AMSB3CTL_P	6
+
+/* EBIU_MBSCTL Masks */
+#define AMSB0CTL_MASK	(0x3 << AMSB0CTL_P)	/* Async Memory Bank 0 Control Modes */
+#define AMSB0CTL_NONE	(0x0 << AMSB0CTL_P)	/* Control Mode - 00 - No logic */
+#define AMSB0CTL_ARE	(0x1 << AMSB0CTL_P)	/* Control Mode - 01 - OR-ed with /ARE */
+#define AMSB0CTL_AOE	(0x2 << AMSB0CTL_P)	/* Control Mode - 02 - OR-ed with /AOE */
+#define AMSB0CTL_AWE	(0x3 << AMSB0CTL_P)	/* Control Mode - 03 - OR-ed with /AWE */
+#define AMSB1CTL_MASK	(0x3 << AMSB1CTL_P)	/* Async Memory Bank 1 Control Modes */
+#define AMSB1CTL_NONE	(0x0 << AMSB1CTL_P)	/* Control Mode - 00 - No logic */
+#define AMSB1CTL_ARE	(0x1 << AMSB1CTL_P)	/* Control Mode - 01 - OR-ed with /ARE */
+#define AMSB1CTL_AOE	(0x2 << AMSB1CTL_P)	/* Control Mode - 02 - OR-ed with /AOE */
+#define AMSB1CTL_AWE	(0x3 << AMSB1CTL_P)	/* Control Mode - 03 - OR-ed with /AWE */
+#define AMSB2CTL_MASK	(0x3 << AMSB2CTL_P)	/* Async Memory Bank 2 Control Modes */
+#define AMSB2CTL_NONE	(0x0 << AMSB2CTL_P)	/* Control Mode - 00 - No logic */
+#define AMSB2CTL_ARE	(0x1 << AMSB2CTL_P)	/* Control Mode - 01 - OR-ed with /ARE */
+#define AMSB2CTL_AOE	(0x2 << AMSB2CTL_P)	/* Control Mode - 02 - OR-ed with /AOE */
+#define AMSB2CTL_AWE	(0x3 << AMSB2CTL_P)	/* Control Mode - 03 - OR-ed with /AWE */
+#define AMSB3CTL_MASK	(0x3 << AMSB3CTL_P)	/* Async Memory Bank 3 Control Modes */
+#define AMSB3CTL_NONE	(0x0 << AMSB3CTL_P)	/* Control Mode - 00 - No logic */
+#define AMSB3CTL_ARE	(0x1 << AMSB3CTL_P)	/* Control Mode - 01 - OR-ed with /ARE */
+#define AMSB3CTL_AOE	(0x2 << AMSB3CTL_P)	/* Control Mode - 02 - OR-ed with /AOE */
+#define AMSB3CTL_AWE	(0x3 << AMSB3CTL_P)	/* Control Mode - 03 - OR-ed with /AWE */
+
+/* EBIU_MODE Bit Positions */
+#define B0MODE_P	0
+#define B1MODE_P	2
+#define B2MODE_P	4
+#define B3MODE_P	6
+
+/* EBIU_MODE Masks */
+#define B0MODE_MASK	(0x3 << B0MODE_P)	/* Async Memory Bank 0 Access Mode */
+#define B0MODE_ASYNC	(0x0 << B0MODE_P)	/* Access Mode - 00 - Asynchronous Mode */
+#define B0MODE_FLASH	(0x1 << B0MODE_P)	/* Access Mode - 01 - Asynchronous Flash Mode */
+#define B0MODE_PAGE	(0x2 << B0MODE_P)	/* Access Mode - 10 - Asynchronous Page Mode */
+#define B0MODE_BURST	(0x3 << B0MODE_P)	/* Access Mode - 11 - Synchronous (Burst) Mode */
+#define B1MODE_MASK	(0x3 << B1MODE_P)	/* Async Memory Bank 1 Access Mode */
+#define B1MODE_ASYNC	(0x0 << B1MODE_P)	/* Access Mode - 00 - Asynchronous Mode */
+#define B1MODE_FLASH	(0x1 << B1MODE_P)	/* Access Mode - 01 - Asynchronous Flash Mode */
+#define B1MODE_PAGE	(0x2 << B1MODE_P)	/* Access Mode - 10 - Asynchronous Page Mode */
+#define B1MODE_BURST	(0x3 << B1MODE_P)	/* Access Mode - 11 - Synchronous (Burst) Mode */
+#define B2MODE_MASK	(0x3 << B2MODE_P)	/* Async Memory Bank 2 Access Mode */
+#define B2MODE_ASYNC	(0x0 << B2MODE_P)	/* Access Mode - 00 - Asynchronous Mode */
+#define B2MODE_FLASH	(0x1 << B2MODE_P)	/* Access Mode - 01 - Asynchronous Flash Mode */
+#define B2MODE_PAGE	(0x2 << B2MODE_P)	/* Access Mode - 10 - Asynchronous Page Mode */
+#define B2MODE_BURST	(0x3 << B2MODE_P)	/* Access Mode - 11 - Synchronous (Burst) Mode */
+#define B3MODE_MASK	(0x3 << B3MODE_P)	/* Async Memory Bank 3 Access Mode */
+#define B3MODE_ASYNC	(0x0 << B3MODE_P)	/* Access Mode - 00 - Asynchronous Mode */
+#define B3MODE_FLASH	(0x1 << B3MODE_P)	/* Access Mode - 01 - Asynchronous Flash Mode */
+#define B3MODE_PAGE	(0x2 << B3MODE_P)	/* Access Mode - 10 - Asynchronous Page Mode */
+#define B3MODE_BURST	(0x3 << B3MODE_P)	/* Access Mode - 11 - Synchronous (Burst) Mode */
+
+/* EBIU_FCTL Bit Positions */
+#define TESTSETLOCK_P	0
+#define BCLK_P		1
+#define PGWS_P		3
+#define PGSZ_P		6
+#define RDDL_P		7
+
+/* EBIU_FCTL Masks */
+#define TESTSETLOCK	(0x1 << TESTSETLOCK_P)	/* Test set lock */
+#define BCLK_MASK	(0x3 << BCLK_P)		/* Burst clock frequency */
+#define BCLK_2		(0x1 << BCLK_P)		/* Burst clock frequency - SCLK/2 */
+#define BCLK_3		(0x2 << BCLK_P)		/* Burst clock frequency - SCLK/3 */
+#define BCLK_4		(0x3 << BCLK_P)		/* Burst clock frequency - SCLK/4 */
+#define PGWS_MASK	(0x7 << PGWS_P)		/* Page wait states */
+#define PGWS_0		(0x0 << PGWS_P)		/* Page wait states - 0 cycles */
+#define PGWS_1		(0x1 << PGWS_P)		/* Page wait states - 1 cycles */
+#define PGWS_2		(0x2 << PGWS_P)		/* Page wait states - 2 cycles */
+#define PGWS_3		(0x3 << PGWS_P)		/* Page wait states - 3 cycles */
+#define PGWS_4		(0x4 << PGWS_P)		/* Page wait states - 4 cycles */
+#define PGSZ		(0x1 << PGSZ_P)		/* Page size */
+#define PGSZ_4		(0x0 << PGSZ_P)		/* Page size - 4 words */
+#define PGSZ_8		(0x1 << PGSZ_P)		/* Page size - 8 words */
+#define RDDL		(0x38 << RDDL_P)	/* Read data delay */
+
+/* EBIU_ARBSTAT Masks */
+#define ARBSTAT		0x00000001	/* Arbitration status */
+#define BGSTAT		0x00000002	/* External Bus grant status */
+
+#endif /* EBIU_MODE */
+
+/* Only available on SDRAM based-parts */
+#ifdef EBIU_SDGCTL
+
+/* EBIU_SDGCTL Masks */
+#define SCTLE		0x00000001	/* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
+#define SCK1E		0x00000002	/* Enable CLKOUT, /SCLK1 */
+#define CL_2		0x00000008	/* SDRAM CAS latency = 2 cycles */
+#define CL_3		0x0000000C	/* SDRAM CAS latency = 3 cycles */
+#define PASR_ALL	0x00000000	/* All 4 SDRAM Banks Refreshed In Self-Refresh */
+#define PASR_B0_B1	0x00000010	/* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
+#define PASR_B0		0x00000020	/* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
+#define TRAS_1		0x00000040	/* SDRAM tRAS = 1 cycle */
+#define TRAS_2		0x00000080	/* SDRAM tRAS = 2 cycles */
+#define TRAS_3		0x000000C0	/* SDRAM tRAS = 3 cycles */
+#define TRAS_4		0x00000100	/* SDRAM tRAS = 4 cycles */
+#define TRAS_5		0x00000140	/* SDRAM tRAS = 5 cycles */
+#define TRAS_6		0x00000180	/* SDRAM tRAS = 6 cycles */
+#define TRAS_7		0x000001C0	/* SDRAM tRAS = 7 cycles */
+#define TRAS_8		0x00000200	/* SDRAM tRAS = 8 cycles */
+#define TRAS_9		0x00000240	/* SDRAM tRAS = 9 cycles */
+#define TRAS_10		0x00000280	/* SDRAM tRAS = 10 cycles */
+#define TRAS_11		0x000002C0	/* SDRAM tRAS = 11 cycles */
+#define TRAS_12		0x00000300	/* SDRAM tRAS = 12 cycles */
+#define TRAS_13		0x00000340	/* SDRAM tRAS = 13 cycles */
+#define TRAS_14		0x00000380	/* SDRAM tRAS = 14 cycles */
+#define TRAS_15		0x000003C0	/* SDRAM tRAS = 15 cycles */
+#define TRP_1		0x00000800	/* SDRAM tRP = 1 cycle */
+#define TRP_2		0x00001000	/* SDRAM tRP = 2 cycles */
+#define TRP_3		0x00001800	/* SDRAM tRP = 3 cycles */
+#define TRP_4		0x00002000	/* SDRAM tRP = 4 cycles */
+#define TRP_5		0x00002800	/* SDRAM tRP = 5 cycles */
+#define TRP_6		0x00003000	/* SDRAM tRP = 6 cycles */
+#define TRP_7		0x00003800	/* SDRAM tRP = 7 cycles */
+#define TRCD_1		0x00008000	/* SDRAM tRCD = 1 cycle */
+#define TRCD_2		0x00010000	/* SDRAM tRCD = 2 cycles */
+#define TRCD_3		0x00018000	/* SDRAM tRCD = 3 cycles */
+#define TRCD_4		0x00020000	/* SDRAM tRCD = 4 cycles */
+#define TRCD_5		0x00028000	/* SDRAM tRCD = 5 cycles */
+#define TRCD_6		0x00030000	/* SDRAM tRCD = 6 cycles */
+#define TRCD_7		0x00038000	/* SDRAM tRCD = 7 cycles */
+#define TWR_1		0x00080000	/* SDRAM tWR = 1 cycle */
+#define TWR_2		0x00100000	/* SDRAM tWR = 2 cycles */
+#define TWR_3		0x00180000	/* SDRAM tWR = 3 cycles */
+#define PUPSD		0x00200000	/* Power-up start delay */
+#define PSM		0x00400000	/* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
+#define PSS		0x00800000	/* enable SDRAM power-up sequence on next SDRAM access */
+#define SRFS		0x01000000	/* Start SDRAM self-refresh mode */
+#define EBUFE		0x02000000	/* Enable external buffering timing */
+#define FBBRW		0x04000000	/* Fast back-to-back read write enable */
+#define EMREN		0x10000000	/* Extended mode register enable */
+#define TCSR		0x20000000	/* Temp compensated self refresh value 85 deg C */
+#define CDDBG		0x40000000	/* Tristate SDRAM controls during bus grant */
+
+/* EBIU_SDBCTL Masks */
+#define EBE		0x0001		/* Enable SDRAM External Bank */
+#define EBSZ_16		0x0000		/* SDRAM External Bank Size = 16MB */
+#define EBSZ_32		0x0002		/* SDRAM External Bank Size = 32MB */
+#define EBSZ_64		0x0004		/* SDRAM External Bank Size = 64MB */
+#define EBSZ_128	0x0006		/* SDRAM External Bank Size = 128MB */
+#define EBSZ_256	0x0007		/* SDRAM External Bank Size = 256MB */
+#define EBSZ_512	0x0008		/* SDRAM External Bank Size = 512MB */
+#define EBCAW_8		0x0000		/* SDRAM External Bank Column Address Width = 8 Bits */
+#define EBCAW_9		0x0010		/* SDRAM External Bank Column Address Width = 9 Bits */
+#define EBCAW_10	0x0020		/* SDRAM External Bank Column Address Width = 10 Bits */
+#define EBCAW_11	0x0030		/* SDRAM External Bank Column Address Width = 11 Bits */
+
+#ifdef __ADSPBF561__
+
+#define EB0E		(EBE<<0)	/* Enable SDRAM external bank 0 */
+#define EB0SZ_16	(EBSZ_16<<0)	/* SDRAM external bank size = 16MB */
+#define EB0SZ_32	(EBSZ_32<<0)	/* SDRAM external bank size = 32MB */
+#define EB0SZ_64	(EBSZ_64<<0)	/* SDRAM external bank size = 64MB */
+#define EB0SZ_128	(EBSZ_128<<0)	/* SDRAM external bank size = 128MB */
+#define EB0CAW_8	(EBCAW_8<<0)	/* SDRAM external bank column address width = 8 bits */
+#define EB0CAW_9	(EBCAW_9<<0)	/* SDRAM external bank column address width = 9 bits */
+#define EB0CAW_10	(EBCAW_10<<0)	/* SDRAM external bank column address width = 9 bits */
+#define EB0CAW_11	(EBCAW_11<<0)	/* SDRAM external bank column address width = 9 bits */
+
+#define EB1E		(EBE<<8)	/* Enable SDRAM external bank 0 */
+#define EB1SZ_16	(EBSZ_16<<8)	/* SDRAM external bank size = 16MB */
+#define EB1SZ_32	(EBSZ_32<<8)	/* SDRAM external bank size = 32MB */
+#define EB1SZ_64	(EBSZ_64<<8)	/* SDRAM external bank size = 64MB */
+#define EB1SZ_128	(EBSZ_128<<8)	/* SDRAM external bank size = 128MB */
+#define EB1CAW_8	(EBCAW_8<<8)	/* SDRAM external bank column address width = 8 bits */
+#define EB1CAW_9	(EBCAW_9<<8)	/* SDRAM external bank column address width = 9 bits */
+#define EB1CAW_10	(EBCAW_10<<8)	/* SDRAM external bank column address width = 9 bits */
+#define EB1CAW_11	(EBCAW_11<<8)	/* SDRAM external bank column address width = 9 bits */
+
+#define EB2E		(EBE<<16)	/* Enable SDRAM external bank 0 */
+#define EB2SZ_16	(EBSZ_16<<16)	/* SDRAM external bank size = 16MB */
+#define EB2SZ_32	(EBSZ_32<<16)	/* SDRAM external bank size = 32MB */
+#define EB2SZ_64	(EBSZ_64<<16)	/* SDRAM external bank size = 64MB */
+#define EB2SZ_128	(EBSZ_128<<16)	/* SDRAM external bank size = 128MB */
+#define EB2CAW_8	(EBCAW_8<<16)	/* SDRAM external bank column address width = 8 bits */
+#define EB2CAW_9	(EBCAW_9<<16)	/* SDRAM external bank column address width = 9 bits */
+#define EB2CAW_10	(EBCAW_10<<16)	/* SDRAM external bank column address width = 9 bits */
+#define EB2CAW_11	(EBCAW_11<<16)	/* SDRAM external bank column address width = 9 bits */
+
+#define EB3E		(EBE<<24)	/* Enable SDRAM external bank 0 */
+#define EB3SZ_16	(EBSZ_16<<24)	/* SDRAM external bank size = 16MB */
+#define EB3SZ_32	(EBSZ_32<<24)	/* SDRAM external bank size = 32MB */
+#define EB3SZ_64	(EBSZ_64<<24)	/* SDRAM external bank size = 64MB */
+#define EB3SZ_128	(EBSZ_128<<24)	/* SDRAM external bank size = 128MB */
+#define EB3CAW_8	(EBCAW_8<<24)	/* SDRAM external bank column address width = 8 bits */
+#define EB3CAW_9	(EBCAW_9<<24)	/* SDRAM external bank column address width = 9 bits */
+#define EB3CAW_10	(EBCAW_10<<24)	/* SDRAM external bank column address width = 9 bits */
+#define EB3CAW_11	(EBCAW_11<<24)	/* SDRAM external bank column address width = 9 bits */
+
+#endif /* BF561 */
+
+/* EBIU_SDSTAT Masks */
+#define SDCI		0x0001		/* SDRAM controller is idle */
+#define SDSRA		0x0002		/* SDRAM SDRAM self refresh is active */
+#define SDPUA		0x0004		/* SDRAM power up active */
+#define SDRS		0x0008		/* SDRAM is in reset state */
+#define SDEASE		0x0010		/* SDRAM EAB sticky error status - W1C */
+#define BGSTAT		0x0020		/* Bus granted */
+
+#endif /* EBIU_SDGCTL */
+
+#endif
diff --git a/include/asm-blackfin/mach-common/bits/emac.h b/include/asm-blackfin/mach-common/bits/emac.h
new file mode 100644
index 0000000..7a43bbb
--- /dev/null
+++ b/include/asm-blackfin/mach-common/bits/emac.h
@@ -0,0 +1,220 @@
+/*
+ * Ethernet MAC Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_EMAC__
+#define __BFIN_PERIPHERAL_EMAC__
+
+/* EMAC_OPMODE Masks */
+#define	RE		0x00000001	/* Receiver Enable */
+#define	ASTP		0x00000002	/* Enable Automatic Pad Stripping On RX Frames */
+#define	HU		0x00000010	/* Hash Filter Unicast Address */
+#define	HM		0x00000020	/* Hash Filter Multicast Address */
+#define	PAM		0x00000040	/* Pass-All-Multicast Mode Enable */
+#define	PR		0x00000080	/* Promiscuous Mode Enable */
+#define	IFE		0x00000100	/* Inverse Filtering Enable */
+#define	DBF		0x00000200	/* Disable Broadcast Frame Reception */
+#define	PBF		0x00000400	/* Pass Bad Frames Enable */
+#define	PSF		0x00000800	/* Pass Short Frames Enable */
+#define	RAF		0x00001000	/* Receive-All Mode */
+#define	TE		0x00010000	/* Transmitter Enable */
+#define	DTXPAD		0x00020000	/* Disable Automatic TX Padding */
+#define	DTXCRC		0x00040000	/* Disable Automatic TX CRC Generation */
+#define	DC		0x00080000	/* Deferral Check */
+#define	BOLMT		0x00300000	/* Back-Off Limit */
+#define	BOLMT_10	0x00000000	/* 10-bit range */
+#define	BOLMT_8		0x00100000	/* 8-bit range */
+#define	BOLMT_4		0x00200000	/* 4-bit range */
+#define	BOLMT_1		0x00300000	/* 1-bit range */
+#define	DRTY		0x00400000	/* Disable TX Retry On Collision */
+#define	LCTRE		0x00800000	/* Enable TX Retry On Late Collision */
+#define	RMII		0x01000000	/* RMII/MII* Mode */
+#define	RMII_10		0x02000000	/* Speed Select for RMII Port (10MBit/100MBit*) */
+#define	FDMODE		0x04000000	/* Duplex Mode Enable (Full/Half*) */
+#define	LB		0x08000000	/* Internal Loopback Enable */
+#define	DRO		0x10000000	/* Disable Receive Own Frames (Half-Duplex Mode) */
+
+/* EMAC_STAADD Masks */
+#define	STABUSY		0x00000001	/* Initiate Station Mgt Reg Access / STA Busy Stat */
+#define	STAOP		0x00000002	/* Station Management Operation Code (Write/Read*) */
+#define	STADISPRE	0x00000004	/* Disable Preamble Generation */
+#define	STAIE		0x00000008	/* Station Mgt. Transfer Done Interrupt Enable */
+#define	REGAD		0x000007C0	/* STA Register Address */
+#define	PHYAD		0x0000F800	/* PHY Device Address */
+
+#define	SET_REGAD(x)	(((x) & 0x1F) <<  6)	/* Set STA Register Address */
+#define	SET_PHYAD(x)	(((x) & 0x1F) << 11)	/* Set PHY Device Address */
+
+/* EMAC_STADAT Mask */
+#define	STADATA		0x0000FFFF	/* Station Management Data */
+
+/* EMAC_FLC Masks */
+#define	FLCBUSY		0x00000001	/* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
+#define	FLCE		0x00000002	/* Flow Control Enable */
+#define	PCF		0x00000004	/* Pass Control Frames */
+#define	BKPRSEN		0x00000008	/* Enable Backpressure */
+#define	FLCPAUSE	0xFFFF0000	/* Pause Time */
+
+#define	SET_FLCPAUSE(x)	(((x) & 0xFFFF) << 16)	/* Set Pause Time */
+
+/* EMAC_WKUP_CTL Masks */
+#define	CAPWKFRM	0x00000001	/* Capture Wake-Up Frames */
+#define	MPKE		0x00000002	/* Magic Packet Enable */
+#define	RWKE		0x00000004	/* Remote Wake-Up Frame Enable */
+#define	GUWKE		0x00000008	/* Global Unicast Wake Enable */
+#define	MPKS		0x00000020	/* Magic Packet Received Status */
+#define	RWKS		0x00000F00	/* Wake-Up Frame Received Status, Filters 3:0 */
+
+/* EMAC_WKUP_FFCMD Masks */
+#define	WF0_E		0x00000001	/* Enable Wake-Up Filter 0 */
+#define	WF0_T		0x00000008	/* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
+#define	WF1_E		0x00000100	/* Enable Wake-Up Filter 1 */
+#define	WF1_T		0x00000800	/* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
+#define	WF2_E		0x00010000	/* Enable Wake-Up Filter 2 */
+#define	WF2_T		0x00080000	/* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
+#define	WF3_E		0x01000000	/* Enable Wake-Up Filter 3 */
+#define	WF3_T		0x08000000	/* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
+
+/* EMAC_WKUP_FFOFF Masks */
+#define	WF0_OFF		0x000000FF	/* Wake-Up Filter 0 Pattern Offset */
+#define	WF1_OFF		0x0000FF00	/* Wake-Up Filter 1 Pattern Offset */
+#define	WF2_OFF		0x00FF0000	/* Wake-Up Filter 2 Pattern Offset */
+#define	WF3_OFF		0xFF000000	/* Wake-Up Filter 3 Pattern Offset */
+
+#define	SET_WF0_OFF(x)	(((x) & 0xFF) <<  0)	/* Set Wake-Up Filter 0 Byte Offset */
+#define	SET_WF1_OFF(x)	(((x) & 0xFF) <<  8)	/* Set Wake-Up Filter 1 Byte Offset */
+#define	SET_WF2_OFF(x)	(((x) & 0xFF) << 16)	/* Set Wake-Up Filter 2 Byte Offset */
+#define	SET_WF3_OFF(x)	(((x) & 0xFF) << 24)	/* Set Wake-Up Filter 3 Byte Offset */
+/* Set ALL Offsets */
+#define	SET_WF_OFFS(x0,x1,x2,x3)	(SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
+
+/* EMAC_WKUP_FFCRC0 Masks */
+#define	WF0_CRC		0x0000FFFF	/* Wake-Up Filter 0 Pattern CRC */
+#define	WF1_CRC		0xFFFF0000	/* Wake-Up Filter 1 Pattern CRC */
+
+#define	SET_WF0_CRC(x)	(((x) & 0xFFFF) << 0)	/* Set Wake-Up Filter 0 Target CRC */
+#define	SET_WF1_CRC(x)	(((x) & 0xFFFF) << 16)	/* Set Wake-Up Filter 1 Target CRC */
+
+/* EMAC_WKUP_FFCRC1 Masks */
+#define	WF2_CRC		0x0000FFFF	/* Wake-Up Filter 2 Pattern CRC */
+#define	WF3_CRC		0xFFFF0000	/* Wake-Up Filter 3 Pattern CRC */
+
+#define	SET_WF2_CRC(x)	(((x) & 0xFFFF) << 0)	/* Set Wake-Up Filter 2 Target CRC */
+#define	SET_WF3_CRC(x)	(((x) & 0xFFFF) << 16)	/* Set Wake-Up Filter 3 Target CRC */
+
+/* EMAC_SYSCTL Masks */
+#define	PHYIE		0x00000001	/* PHY_INT Interrupt Enable */
+#define	RXDWA		0x00000002	/* Receive Frame DMA Word Alignment (Odd/Even*) */
+#define	RXCKS		0x00000004	/* Enable RX Frame TCP/UDP Checksum Computation */
+#define	MDCDIV		0x00003F00	/* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
+
+#define	SET_MDCDIV(x)	(((x) & 0x3F) << 8)	/* Set MDC Clock Divisor */
+
+/* EMAC_SYSTAT Masks */
+#define	PHYINT		0x00000001	/* PHY_INT Interrupt Status */
+#define	MMCINT		0x00000002	/* MMC Counter Interrupt Status */
+#define	RXFSINT		0x00000004	/* RX Frame-Status Interrupt Status */
+#define	TXFSINT		0x00000008	/* TX Frame-Status Interrupt Status */
+#define	WAKEDET		0x00000010	/* Wake-Up Detected Status */
+#define	RXDMAERR	0x00000020	/* RX DMA Direction Error Status */
+#define	TXDMAERR	0x00000040	/* TX DMA Direction Error Status */
+#define	STMDONE		0x00000080	/* Station Mgt. Transfer Done Interrupt Status */
+
+/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
+#define	RX_FRLEN	0x000007FF	/* Frame Length In Bytes */
+#define	RX_COMP		0x00001000	/* RX Frame Complete */
+#define	RX_OK		0x00002000	/* RX Frame Received With No Errors */
+#define	RX_LONG		0x00004000	/* RX Frame Too Long Error */
+#define	RX_ALIGN	0x00008000	/* RX Frame Alignment Error */
+#define	RX_CRC		0x00010000	/* RX Frame CRC Error */
+#define	RX_LEN		0x00020000	/* RX Frame Length Error */
+#define	RX_FRAG		0x00040000	/* RX Frame Fragment Error */
+#define	RX_ADDR		0x00080000	/* RX Frame Address Filter Failed Error */
+#define	RX_DMAO		0x00100000	/* RX Frame DMA Overrun Error */
+#define	RX_PHY		0x00200000	/* RX Frame PHY Error */
+#define	RX_LATE		0x00400000	/* RX Frame Late Collision Error */
+#define	RX_RANGE	0x00800000	/* RX Frame Length Field Out of Range Error */
+#define	RX_MULTI	0x01000000	/* RX Multicast Frame Indicator */
+#define	RX_BROAD	0x02000000	/* RX Broadcast Frame Indicator */
+#define	RX_CTL		0x04000000	/* RX Control Frame Indicator */
+#define	RX_UCTL		0x08000000	/* Unsupported RX Control Frame Indicator */
+#define	RX_TYPE		0x10000000	/* RX Typed Frame Indicator */
+#define	RX_VLAN1	0x20000000	/* RX VLAN1 Frame Indicator */
+#define	RX_VLAN2	0x40000000	/* RX VLAN2 Frame Indicator */
+#define	RX_ACCEPT	0x80000000	/* RX Frame Accepted Indicator */
+
+/*  EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
+#define	TX_COMP		0x00000001	/* TX Frame Complete */
+#define	TX_OK		0x00000002	/* TX Frame Sent With No Errors */
+#define	TX_ECOLL	0x00000004	/* TX Frame Excessive Collision Error */
+#define	TX_LATE		0x00000008	/* TX Frame Late Collision Error */
+#define	TX_DMAU		0x00000010	/* TX Frame DMA Underrun Error (STAT) */
+#define	TX_MACE		0x00000010	/* Internal MAC Error Detected (STKY and IRQE) */
+#define	TX_EDEFER	0x00000020	/* TX Frame Excessive Deferral Error */
+#define	TX_BROAD	0x00000040	/* TX Broadcast Frame Indicator */
+#define	TX_MULTI	0x00000080	/* TX Multicast Frame Indicator */
+#define	TX_CCNT		0x00000F00	/* TX Frame Collision Count */
+#define	TX_DEFER	0x00001000	/* TX Frame Deferred Indicator */
+#define	TX_CRS		0x00002000	/* TX Frame Carrier Sense Not Asserted Error */
+#define	TX_LOSS		0x00004000	/* TX Frame Carrier Lost During TX Error */
+#define	TX_RETRY	0x00008000	/* TX Frame Successful After Retry */
+#define	TX_FRLEN	0x07FF0000	/* TX Frame Length (Bytes) */
+
+/* EMAC_MMC_CTL Masks */
+#define	RSTC		0x00000001	/* Reset All Counters */
+#define	CROLL		0x00000002	/* Counter Roll-Over Enable */
+#define	CCOR		0x00000004	/* Counter Clear-On-Read Mode Enable */
+#define	MMCE		0x00000008	/* Enable MMC Counter Operation */
+
+/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
+#define	RX_OK_CNT	0x00000001	/* RX Frames Received With No Errors */
+#define	RX_FCS_CNT	0x00000002	/* RX Frames W/Frame Check Sequence Errors */
+#define	RX_ALIGN_CNT	0x00000004	/* RX Frames With Alignment Errors */
+#define	RX_OCTET_CNT	0x00000008	/* RX Octets Received OK */
+#define	RX_LOST_CNT	0x00000010	/* RX Frames Lost Due To Internal MAC RX Error */
+#define	RX_UNI_CNT	0x00000020	/* Unicast RX Frames Received OK */
+#define	RX_MULTI_CNT	0x00000040	/* Multicast RX Frames Received OK */
+#define	RX_BROAD_CNT	0x00000080	/* Broadcast RX Frames Received OK */
+#define	RX_IRL_CNT	0x00000100	/* RX Frames With In-Range Length Errors */
+#define	RX_ORL_CNT	0x00000200	/* RX Frames With Out-Of-Range Length Errors */
+#define	RX_LONG_CNT	0x00000400	/* RX Frames With Frame Too Long Errors */
+#define	RX_MACCTL_CNT	0x00000800	/* MAC Control RX Frames Received */
+#define	RX_OPCODE_CTL	0x00001000	/* Unsupported Op-Code RX Frames Received */
+#define	RX_PAUSE_CNT	0x00002000	/* PAUSEMAC Control RX Frames Received */
+#define	RX_ALLF_CNT	0x00004000	/* All RX Frames Received */
+#define	RX_ALLO_CNT	0x00008000	/* All RX Octets Received */
+#define	RX_TYPED_CNT	0x00010000	/* Typed RX Frames Received */
+#define	RX_SHORT_CNT	0x00020000	/* RX Frame Fragments (< 64 Bytes) Received */
+#define	RX_EQ64_CNT	0x00040000	/* 64-Byte RX Frames Received */
+#define	RX_LT128_CNT	0x00080000	/* 65-127-Byte RX Frames Received */
+#define	RX_LT256_CNT	0x00100000	/* 128-255-Byte RX Frames Received */
+#define	RX_LT512_CNT	0x00200000	/* 256-511-Byte RX Frames Received */
+#define	RX_LT1024_CNT	0x00400000	/* 512-1023-Byte RX Frames Received */
+#define	RX_GE1024_CNT	0x00800000	/* 1024-Max-Byte RX Frames Received */
+
+/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
+#define	TX_OK_CNT	0x00000001	/* TX Frames Sent OK */
+#define	TX_SCOLL_CNT	0x00000002	/* TX Frames With Single Collisions */
+#define	TX_MCOLL_CNT	0x00000004	/* TX Frames With Multiple Collisions */
+#define	TX_OCTET_CNT	0x00000008	/* TX Octets Sent OK */
+#define	TX_DEFER_CNT	0x00000010	/* TX Frames With Deferred Transmission */
+#define	TX_LATE_CNT	0x00000020	/* TX Frames With Late Collisions */
+#define	TX_ABORTC_CNT	0x00000040	/* TX Frames Aborted Due To Excess Collisions */
+#define	TX_LOST_CNT	0x00000080	/* TX Frames Lost Due To Internal MAC TX Error */
+#define	TX_CRS_CNT	0x00000100	/* TX Frames With Carrier Sense Errors */
+#define	TX_UNI_CNT	0x00000200	/* Unicast TX Frames Sent */
+#define	TX_MULTI_CNT	0x00000400	/* Multicast TX Frames Sent */
+#define	TX_BROAD_CNT	0x00000800	/* Broadcast TX Frames Sent */
+#define	TX_EXDEF_CTL	0x00001000	/* TX Frames With Excessive Deferral */
+#define	TX_MACCTL_CNT	0x00002000	/* MAC Control TX Frames Sent */
+#define	TX_ALLF_CNT	0x00004000	/* All TX Frames Sent */
+#define	TX_ALLO_CNT	0x00008000	/* All TX Octets Sent */
+#define	TX_EQ64_CNT	0x00010000	/* 64-Byte TX Frames Sent */
+#define	TX_LT128_CNT	0x00020000	/* 65-127-Byte TX Frames Sent */
+#define	TX_LT256_CNT	0x00040000	/* 128-255-Byte TX Frames Sent */
+#define	TX_LT512_CNT	0x00080000	/* 256-511-Byte TX Frames Sent */
+#define	TX_LT1024_CNT	0x00100000	/* 512-1023-Byte TX Frames Sent */
+#define	TX_GE1024_CNT	0x00200000	/* 1024-Max-Byte TX Frames Sent */
+#define	TX_ABORT_CNT	0x00400000	/* TX Frames Aborted */
+
+#endif
diff --git a/include/asm-blackfin/mach-common/bits/eppi.h b/include/asm-blackfin/mach-common/bits/eppi.h
new file mode 100644
index 0000000..fb1456f
--- /dev/null
+++ b/include/asm-blackfin/mach-common/bits/eppi.h
@@ -0,0 +1,70 @@
+/*
+ * Enhanced PPI (EPPI)
+ */
+
+#ifndef __BFIN_PERIPHERAL_EPPI__
+#define __BFIN_PERIPHERAL_EPPI__
+
+/* Bit masks for EPPIx_STATUS */
+#define CFIFO_ERR              0x0001        /* Chroma FIFO Error */
+#define YFIFO_ERR              0x0002        /* Luma FIFO Error */
+#define LTERR_OVR              0x0004        /* Line Track Overflow */
+#define LTERR_UNDR             0x0008        /* Line Track Underflow */
+#define FTERR_OVR              0x0010        /* Frame Track Overflow */
+#define FTERR_UNDR             0x0020        /* Frame Track Underflow */
+#define ERR_NCOR               0x0040        /* Preamble Error Not Corrected */
+#define DMA1URQ                0x0080        /* DMA1 Urgent Request */
+#define DMA0URQ                0x0100        /* DMA0 Urgent Request */
+#define ERR_DET                0x4000        /* Preamble Error Detected */
+#define FLD                    0x8000        /* Field */
+
+/* Bit masks for EPPIx_CONTROL */
+#define EPPI_EN                0x00000001    /* Enable */
+#define EPPI_DIR               0x00000002    /* Direction */
+#define XFR_TYPE               0x0000000c    /* Operating Mode */
+#define FS_CFG                 0x00000030    /* Frame Sync Configuration */
+#define FLD_SEL                0x00000040    /* Field Select/Trigger */
+#define ITU_TYPE               0x00000080    /* ITU Interlaced or Progressive */
+#define BLANKGEN               0x00000100    /* ITU Output Mode with Internal Blanking Generation */
+#define ICLKGEN                0x00000200    /* Internal Clock Generation */
+#define IFSGEN                 0x00000400    /* Internal Frame Sync Generation */
+#define POLC                   0x00001800    /* Frame Sync and Data Driving/Sampling Edges */
+#define POLS                   0x00006000    /* Frame Sync Polarity */
+#define DLENGTH                0x00038000    /* Data Length */
+#define SKIP_EN                0x00040000    /* Skip Enable */
+#define SKIP_EO                0x00080000    /* Skip Even or Odd */
+#define PACKEN                 0x00100000    /* Packing/Unpacking Enable */
+#define SWAPEN                 0x00200000    /* Swap Enable */
+#define SIGN_EXT               0x00400000    /* Sign Extension or Zero-filled / Data Split Format */
+#define SPLT_EVEN_ODD          0x00800000    /* Split Even and Odd Data Samples */
+#define SUBSPLT_ODD            0x01000000    /* Sub-split Odd Samples */
+#define DMACFG                 0x02000000    /* One or Two DMA Channels Mode */
+#define RGB_FMT_EN             0x04000000    /* RGB Formatting Enable */
+#define FIFO_RWM               0x18000000    /* FIFO Regular Watermarks */
+#define FIFO_UWM               0x60000000    /* FIFO Urgent Watermarks */
+
+#define DLEN_8                 (0 << 15)     /* 000 - 8 bits */
+#define DLEN_10                (1 << 15)     /* 001 - 10 bits */
+#define DLEN_12                (2 << 15)     /* 010 - 12 bits */
+#define DLEN_14                (3 << 15)     /* 011 - 14 bits */
+#define DLEN_16                (4 << 15)     /* 100 - 16 bits */
+#define DLEN_18                (5 << 15)     /* 101 - 18 bits */
+#define DLEN_24                (6 << 15)     /* 110 - 24 bits */
+
+/* Bit masks for EPPIx_FS2W_LVB */
+#define F1VB_BD                0x000000ff    /* Vertical Blanking before Field 1 Active Data */
+#define F1VB_AD                0x0000ff00    /* Vertical Blanking after Field 1 Active Data */
+#define F2VB_BD                0x00ff0000    /* Vertical Blanking before Field 2 Active Data */
+#define F2VB_AD                0xff000000    /* Vertical Blanking after Field 2 Active Data */
+
+/* Bit masks for EPPIx_FS2W_LAVF */
+#define F1_ACT                 0x0000ffff    /* Number of Lines of Active Data in Field 1 */
+#define F2_ACT                 0xffff0000    /* Number of Lines of Active Data in Field 2 */
+
+/* Bit masks for EPPIx_CLIP */
+#define LOW_ODD                0x000000ff    /* Lower Limit for Odd Bytes (Chroma) */
+#define HIGH_ODD               0x0000ff00    /* Upper Limit for Odd Bytes (Chroma) */
+#define LOW_EVEN               0x00ff0000    /* Lower Limit for Even Bytes (Luma) */
+#define HIGH_EVEN              0xff000000    /* Upper Limit for Even Bytes (Luma) */
+
+#endif
diff --git a/include/asm-blackfin/mach-common/bits/lockbox.h b/include/asm-blackfin/mach-common/bits/lockbox.h
new file mode 100644
index 0000000..09310e1
--- /dev/null
+++ b/include/asm-blackfin/mach-common/bits/lockbox.h
@@ -0,0 +1,62 @@
+/*
+ * Lockbox/Security Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_LOCKBOX__
+#define __BFIN_PERIPHERAL_LOCKBOX__
+
+#ifndef __ASSEMBLY__
+
+#include "bootrom.h"
+
+/* SESR argument structure. Expected to reside at 0xFF900018. */
+typedef struct SESR_args {
+  unsigned short  usFlags;            /* security firmware flags            */
+  unsigned short  usIRQMask;          /* interrupt mask                     */
+  unsigned long   ulMessageSize;      /* message length in bytes            */
+  unsigned long   ulSFEntryPoint;     /* entry point of secure function     */
+  unsigned long   ulMessagePtr;       /* pointer to the buffer containing
+                                         the digital signature and message  */
+  unsigned long   ulReserved1;        /* reserved                           */
+  unsigned long   ulReserved2;        /* reserved                           */
+} tSESR_args;
+
+/* Secure Entry Service Routine */
+void (* const sesr)(void) = (void *)_BOOTROM_SESR;
+
+#endif
+
+/* SESR flags argument bitfields                                            */
+#define SESR_FLAGS_STAY_AT_NMI              0x0000
+#define SESR_FLAGS_DROP_BELOW_NMI           0x0001
+#define SESR_FLAGS_NO_SF_DMA                0x0000
+#define SESR_FLAGS_DMA_SF_TO_RUN_DEST       0x0002
+#define SESR_FLAGS_USE_ADI_PUB_KEY          0x0000
+#define SESR_FLAGS_USE_CUST_PUB_KEY         0x0100
+
+/* Bit masks for SECURE_SYSSWT */
+#define EMUDABL                0x00000001    /* Emulation Disable */
+#define RSTDABL                0x00000002    /* Reset Disable */
+#define L1IDABL                0x0000001c    /* L1 Instruction Memory Disable */
+#define L1DADABL               0x000000e0    /* L1 Data Bank A Memory Disable */
+#define L1DBDABL               0x00000700    /* L1 Data Bank B Memory Disable */
+#define DMA0OVR                0x00000800    /* DMA0 Memory Access Override */
+#define DMA1OVR                0x00001000    /* DMA1 Memory Access Override */
+#define EMUOVR                 0x00004000    /* Emulation Override */
+#define OTPSEN                 0x00008000    /* OTP Secrets Enable */
+#define L2DABL                 0x00070000    /* L2 Memory Disable */
+
+/* Bit masks for SECURE_CONTROL */
+#define SECURE0                0x0001        /* SECURE 0 */
+#define SECURE1                0x0002        /* SECURE 1 */
+#define SECURE2                0x0004        /* SECURE 2 */
+#define SECURE3                0x0008        /* SECURE 3 */
+
+/* Bit masks for SECURE_STATUS */
+#define SECMODE                0x0003        /* Secured Mode Control State */
+#define NMI                    0x0004        /* Non Maskable Interrupt */
+#define AFVALID                0x0008        /* Authentication Firmware Valid */
+#define AFEXIT                 0x0010        /* Authentication Firmware Exit */
+#define SECSTAT                0x00e0        /* Secure Status */
+
+#endif
diff --git a/include/asm-blackfin/mach-common/bits/mpu.h b/include/asm-blackfin/mach-common/bits/mpu.h
new file mode 100644
index 0000000..39998f8
--- /dev/null
+++ b/include/asm-blackfin/mach-common/bits/mpu.h
@@ -0,0 +1,116 @@
+/*
+ * MPU Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_MPU__
+#define __BFIN_PERIPHERAL_MPU__
+
+/*
+ * DMEM_CONTROL Register
+ */
+
+/* ** Bit Positions */
+#define ENDM_P			0x00	/* (doesn't really exist) Enable Data Memory L1 */
+#define DMCTL_ENDM_P		ENDM_P	/* "" (older define) */
+#define ENDCPLB_P		0x01	/* Enable DCPLBS */
+#define DMCTL_ENDCPLB_P		ENDCPLB_P	/* "" (older define) */
+#define DMC0_P			0x02	/* L1 Data Memory Configure bit 0 */
+#define DMCTL_DMC0_P		DMC0_P	/* "" (older define) */
+#define DMC1_P			0x03	/* L1 Data Memory Configure bit 1 */
+#define DMCTL_DMC1_P		DMC1_P	/* "" (older define) */
+#define DCBS_P			0x04	/* L1 Data Cache Bank Select */
+#define PORT_PREF0_P		0x12	/* DAG0 Port Preference */
+#define PORT_PREF1_P		0x13	/* DAG1 Port Preference */
+
+/* ** Masks */
+#define ENDM			0x00000001	/* (doesn't really exist) Enable Data Memory L1 */
+#define ENDCPLB			0x00000002	/* Enable DCPLB */
+#define ASRAM_BSRAM		0x00000000
+#define ACACHE_BSRAM		0x00000008
+#define ACACHE_BCACHE		0x0000000C
+#define DCBS			0x00000010	/*  L1 Data Cache Bank Select */
+#define PORT_PREF0		0x00001000	/* DAG0 Port Preference */
+#define PORT_PREF1		0x00002000	/* DAG1 Port Preference */
+
+/* IMEM_CONTROL Register */
+/* ** Bit Positions */
+#define ENIM_P			0x00	/* Enable L1 Code Memory */
+#define IMCTL_ENIM_P		0x00	/* "" (older define) */
+#define ENICPLB_P		0x01	/* Enable ICPLB */
+#define IMCTL_ENICPLB_P		0x01	/* "" (older define) */
+#define IMC_P			0x02	/* Enable */
+#define IMCTL_IMC_P		0x02	/* Configure L1 code memory as cache (0=SRAM) */
+#define ILOC0_P			0x03	/* Lock Way 0 */
+#define ILOC1_P			0x04	/* Lock Way 1 */
+#define ILOC2_P			0x05	/* Lock Way 2 */
+#define ILOC3_P			0x06	/* Lock Way 3 */
+#define LRUPRIORST_P		0x0D	/* Least Recently Used Replacement Priority */
+
+/* ** Masks */
+#define ENIM			0x00000001	/* Enable L1 Code Memory */
+#define ENICPLB			0x00000002	/* Enable ICPLB */
+#define IMC			0x00000004	/* Configure L1 code memory as cache (0=SRAM) */
+#define ILOC0			0x00000008	/* Lock Way 0 */
+#define ILOC1			0x00000010	/* Lock Way 1 */
+#define ILOC2			0x00000020	/* Lock Way 2 */
+#define ILOC3			0x00000040	/* Lock Way 3 */
+#define LRUPRIORST		0x00002000	/* Least Recently Used Replacement Priority */
+
+/* DCPLB_DATA and ICPLB_DATA Registers */
+/* ** Bit Positions */
+#define CPLB_VALID_P		0x00000000	/* 0=invalid entry, 1=valid entry */
+#define CPLB_LOCK_P		0x00000001	/* 0=entry may be replaced, 1=entry locked */
+#define CPLB_USER_RD_P		0x00000002	/* 0=no read access, 1=read access allowed (user mode) */
+
+/* ** Masks */
+#define CPLB_VALID		0x00000001	/* 0=invalid entry, 1=valid entry */
+#define CPLB_LOCK		0x00000002	/* 0=entry may be replaced, 1=entry locked */
+#define CPLB_USER_RD		0x00000004	/* 0=no read access, 1=read access allowed (user mode) */
+#define PAGE_SIZE_1KB		0x00000000	/* 1 KB page size */
+#define PAGE_SIZE_4KB		0x00010000	/* 4 KB page size */
+#define PAGE_SIZE_1MB		0x00020000	/* 1 MB page size */
+#define PAGE_SIZE_4MB		0x00030000	/* 4 MB page size */
+#define PAGE_SIZE_MASK		0x00030000	/* the bits for the page_size field */
+#define PAGE_SIZE_SHIFT		16
+#define CPLB_L1SRAM		0x00000020	/* 0=SRAM mapped in L1, 0=SRAM not mapped to L1 */
+#define CPLB_PORTPRIO		0x00000200	/* 0=low priority port, 1= high priority port */
+#define CPLB_L1_CHBL		0x00001000	/* 0=non-cacheable in L1, 1=cacheable in L1 */
+
+/* ICPLB_DATA only */
+#define CPLB_LRUPRIO		0x00000100	/* 0=can be replaced by any line, 1=priority for non-replacement */
+
+/* DCPLB_DATA only */
+#define CPLB_USER_WR		0x00000008	/* 0=no write access, 0=write access allowed (user mode) */
+#define CPLB_SUPV_WR		0x00000010	/* 0=no write access, 0=write access allowed (supervisor mode) */
+#define CPLB_DIRTY		0x00000080	/* 1=dirty, 0=clean */
+#define CPLB_L1_AOW		0x00008000	/* 0=do not allocate cache lines on write-through writes, */
+						/* 1= allocate cache lines on write-through writes. */
+#define CPLB_WT			0x00004000	/* 0=write-back, 1=write-through */
+
+/* ITEST_COMMAND and DTEST_COMMAND Registers */
+/* ** Masks */
+#define TEST_READ		0x00000000	/* Read Access */
+#define TEST_WRITE		0x00000002	/* Write Access */
+#define TEST_TAG		0x00000000	/* Access TAG */
+#define TEST_DATA		0x00000004	/* Access DATA */
+#define TEST_DW0		0x00000000	/* Select Double Word 0 */
+#define TEST_DW1		0x00000008	/* Select Double Word 1 */
+#define TEST_DW2		0x00000010	/* Select Double Word 2 */
+#define TEST_DW3		0x00000018	/* Select Double Word 3 */
+#define TEST_MB0		0x00000000	/* Select Mini-Bank 0 */
+#define TEST_MB1		0x00010000	/* Select Mini-Bank 1 */
+#define TEST_MB2		0x00020000	/* Select Mini-Bank 2 */
+#define TEST_MB3		0x00030000	/* Select Mini-Bank 3 */
+#define TEST_SET(x)		((x << 5) & 0x03E0)	/* Set Index 0->31 */
+#define TEST_WAY0		0x00000000	/* Access Way0 */
+#define TEST_WAY1		0x04000000	/* Access Way1 */
+
+/* ** ITEST_COMMAND only */
+#define TEST_WAY2		0x08000000	/* Access Way2 */
+#define TEST_WAY3		0x0C000000	/* Access Way3 */
+
+/* ** DTEST_COMMAND only */
+#define TEST_BNKSELA		0x00000000	/* Access SuperBank A */
+#define TEST_BNKSELB		0x00800000	/* Access SuperBank B */
+
+#endif
diff --git a/include/asm-blackfin/mach-common/bits/otp.h b/include/asm-blackfin/mach-common/bits/otp.h
new file mode 100644
index 0000000..d529a0a
--- /dev/null
+++ b/include/asm-blackfin/mach-common/bits/otp.h
@@ -0,0 +1,72 @@
+/*
+ * OTP Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_OTP__
+#define __BFIN_PERIPHERAL_OTP__
+
+#ifndef __ASSEMBLY__
+
+#include "bootrom.h"
+
+static uint32_t (* const otp_command)(uint32_t command, uint32_t value) = (void *)_BOOTROM_OTP_COMMAND;
+static uint32_t (* const otp_read)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)_BOOTROM_OTP_READ;
+static uint32_t (* const otp_write)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)_BOOTROM_OTP_WRITE;
+
+#endif
+
+/* otp_command(): defines for "command" */
+#define OTP_INIT             0x00000001
+#define OTP_CLOSE            0x00000002
+
+/* otp_{read,write}(): defines for "flags" */
+#define OTP_LOWER_HALF       0x00000000 /* select upper/lower 64-bit half (bit 0) */
+#define OTP_UPPER_HALF       0x00000001
+#define OTP_NO_ECC           0x00000010 /* do not use ECC */
+#define OTP_LOCK             0x00000020 /* sets page protection bit for page */
+#define OTP_ACCESS_READ      0x00001000
+#define OTP_ACCESS_READWRITE 0x00002000
+
+/* Return values for all functions */
+#define OTP_SUCCESS          0x00000000
+#define OTP_MASTER_ERROR     0x001
+#define OTP_WRITE_ERROR      0x003
+#define OTP_READ_ERROR       0x005
+#define OTP_ACC_VIO_ERROR    0x009
+#define OTP_DATA_MULT_ERROR  0x011
+#define OTP_ECC_MULT_ERROR   0x021
+#define OTP_PREV_WR_ERROR    0x041
+#define OTP_DATA_SB_WARN     0x100
+#define OTP_ECC_SB_WARN      0x200
+
+/* Predefined otp pages: Factory Programmed Settings */
+#define FPS00                0x0004
+#define FPS01                0x0005
+#define FPS02                0x0006
+#define FPS03                0x0007
+#define FPS04                0x0008
+#define FPS05                0x0009
+#define FPS06                0x000A
+#define FPS07                0x000B
+#define FPS08                0x000C
+#define FPS09                0x000D
+#define FPS10                0x000E
+#define FPS11                0x000F
+
+/* Predefined otp pages: Customer Programmed Settings */
+#define CPS00                0x0010
+#define CPS01                0x0011
+#define CPS02                0x0012
+#define CPS03                0x0013
+#define CPS04                0x0014
+#define CPS05                0x0015
+#define CPS06                0x0016
+#define CPS07                0x0017
+
+/* Predefined otp pages: Pre-Boot Settings */
+#define PBS00                0x0018
+#define PBS01                0x0019
+#define PBS02                0x001A
+#define PBS03                0x001B
+
+#endif
diff --git a/include/asm-blackfin/mach-common/bits/pll.h b/include/asm-blackfin/mach-common/bits/pll.h
new file mode 100644
index 0000000..9009f26
--- /dev/null
+++ b/include/asm-blackfin/mach-common/bits/pll.h
@@ -0,0 +1,96 @@
+/*
+ * PLL Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PLL__
+#define __BFIN_PERIPHERAL_PLL__
+
+/* PLL_CTL Masks */
+#define DF			0x0001		/* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
+#define PLL_OFF			0x0002		/* PLL Not Powered */
+#define STOPCK			0x0008		/* Core Clock Off */
+#define PDWN			0x0020		/* Enter Deep Sleep Mode */
+#define IN_DELAY		0x0040		/* Add 200ps Delay To EBIU Input Latches */
+#define OUT_DELAY		0x0080		/* Add 200ps Delay To EBIU Output Signals */
+#define BYPASS			0x0100		/* Bypass the PLL */
+#define MSEL			0x7E00		/* Multiplier Select For CCLK/VCO Factors */
+#define SPORT_HYST		0x8000		/* Enable Additional Hysteresis on SPORT Input Pins */
+
+/* PLL_DIV Masks */
+#define SSEL			0x000F		/* System Select */
+#define CSEL			0x0030		/* Core Select */
+#define CSEL_DIV1		0x0000		/* CCLK = VCO / 1 */
+#define CSEL_DIV2		0x0010		/* CCLK = VCO / 2 */
+#define CSEL_DIV4		0x0020		/* CCLK = VCO / 4 */
+#define CSEL_DIV8		0x0030		/* CCLK = VCO / 8 */
+
+#define CCLK_DIV1		CSEL_DIV1
+#define CCLK_DIV2		CSEL_DIV2
+#define CCLK_DIV4		CSEL_DIV4
+#define CCLK_DIV8		CSEL_DIV8
+
+/* PLL_STAT Masks */
+#define ACTIVE_PLLENABLED	0x0001		/* Processor In Active Mode With PLL Enabled */
+#define FULL_ON			0x0002		/* Processor In Full On Mode */
+#define ACTIVE_PLLDISABLED	0x0004		/* Processor In Active Mode With PLL Disabled */
+#define DEEP_SLEEP		0x0008		/* Processor In Deep Sleep Mode */
+#define SLEEP			0x0010		/* Processor In Sleep Mode */
+#define PLL_LOCKED		0x0020		/* PLL_LOCKCNT Has Been Reached */
+#define CORE_IDLE		0x0040		/* Processor In IDLE Mode */
+#define VSTAT			0x0080		/* Voltage Regulator Has Reached Programmed Voltage */
+
+/* VR_CTL Masks */
+#ifdef __ADSPBF52x__
+#define FREQ_MASK		0x3000		/* Switching Oscillator Frequency For Regulator */
+#define FREQ_HIBERNATE		0x0000		/* Powerdown/Bypass On-Board Regulation */
+#define FREQ_1000		0x3000		/* Switching Frequency Is 1 MHz */
+#else
+#define FREQ_MASK		0x0003		/* Switching Oscillator Frequency For Regulator */
+#define FREQ_HIBERNATE		0x0000		/* Powerdown/Bypass On-Board Regulation */
+#define FREQ_333		0x0001		/* Switching Frequency Is 333 kHz */
+#define FREQ_667		0x0002		/* Switching Frequency Is 667 kHz */
+#define FREQ_1000		0x0003		/* Switching Frequency Is 1 MHz */
+#endif
+
+#define GAIN_MASK		0x000C		/* Voltage Level Gain */
+#define GAIN_5			0x0000		/* GAIN = 5 */
+#define GAIN_10			0x0004		/* GAIN = 10 */
+#define GAIN_20			0x0008		/* GAIN = 20 */
+#define GAIN_50			0x000C		/* GAIN = 50 */
+
+#ifdef __ADSPBF52x__
+#define VLEV_MASK		0x00F0		/* Internal Voltage Level */
+#define VLEV_085		0x0040		/* VLEV = 0.85 V (-5% - +10% Accuracy) */
+#define VLEV_090		0x0050		/* VLEV = 0.90 V (-5% - +10% Accuracy) */
+#define VLEV_095		0x0060		/* VLEV = 0.95 V (-5% - +10% Accuracy) */
+#define VLEV_100		0x0070		/* VLEV = 1.00 V (-5% - +10% Accuracy) */
+#define VLEV_105		0x0080		/* VLEV = 1.05 V (-5% - +10% Accuracy) */
+#define VLEV_110		0x0090		/* VLEV = 1.10 V (-5% - +10% Accuracy) */
+#define VLEV_115		0x00A0		/* VLEV = 1.15 V (-5% - +10% Accuracy) */
+#define VLEV_120		0x00B0		/* VLEV = 1.20 V (-5% - +10% Accuracy) */
+#else
+#define VLEV_MASK		0x00F0		/* Internal Voltage Level */
+#define VLEV_085		0x0060		/* VLEV = 0.85 V (-5% - +10% Accuracy) */
+#define VLEV_090		0x0070		/* VLEV = 0.90 V (-5% - +10% Accuracy) */
+#define VLEV_095		0x0080		/* VLEV = 0.95 V (-5% - +10% Accuracy) */
+#define VLEV_100		0x0090		/* VLEV = 1.00 V (-5% - +10% Accuracy) */
+#define VLEV_105		0x00A0		/* VLEV = 1.05 V (-5% - +10% Accuracy) */
+#define VLEV_110		0x00B0		/* VLEV = 1.10 V (-5% - +10% Accuracy) */
+#define VLEV_115		0x00C0		/* VLEV = 1.15 V (-5% - +10% Accuracy) */
+#define VLEV_120		0x00D0		/* VLEV = 1.20 V (-5% - +10% Accuracy) */
+#define VLEV_125		0x00E0		/* VLEV = 1.25 V (-5% - +10% Accuracy) */
+#define VLEV_130		0x00F0		/* VLEV = 1.30 V (-5% - +10% Accuracy) */
+#endif
+
+#define WAKE			0x0100		/* Enable RTC/Reset Wakeup From Hibernate */
+#define CANWE			0x0200		/* Enable CAN Wakeup From Hibernate */
+#define PHYWE			0x0400		/* Enable PHY Wakeup From Hibernate */
+#define GPWE			0x0400		/* General-purpose Wakeup From Hibernate */
+#define MXVRWE			0x0400		/* MXVR Wakeup From Hibernate */
+#define USBWE			0x0800		/* USB Wakeup From Hibernate */
+#define KPADWE			0x1000		/* Keypad Wakeup From Hibernate */
+#define ROTWE			0x2000		/* Rotary Counter Wakeup From Hibernate */
+#define CLKBUFOE		0x4000		/* CLKIN Buffer Output Enable */
+#define CKELOW			0x8000		/* Enable Drive CKE Low During Reset */
+
+#endif
diff --git a/include/asm-blackfin/mach-common/bits/ppi.h b/include/asm-blackfin/mach-common/bits/ppi.h
new file mode 100644
index 0000000..523f238
--- /dev/null
+++ b/include/asm-blackfin/mach-common/bits/ppi.h
@@ -0,0 +1,38 @@
+/*
+ * PPI Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PPI__
+#define __BFIN_PERIPHERAL_PPI__
+
+/* PPI_CONTROL Masks */
+#define PORT_EN			0x0001	/* PPI Port Enable */
+#define PORT_DIR		0x0002	/* PPI Port Direction */
+#define XFR_TYPE		0x000C	/* PPI Transfer Type */
+#define PORT_CFG		0x0030	/* PPI Port Configuration */
+#define FLD_SEL			0x0040	/* PPI Active Field Select */
+#define PACK_EN			0x0080	/* PPI Packing Mode */
+#define DMA32			0x0100	/* PPI 32-bit DMA Enable */
+#define SKIP_EN			0x0200	/* PPI Skip Element Enable */
+#define SKIP_EO			0x0400	/* PPI Skip Even/Odd Elements */
+#define DLENGTH			0x3800	/* PPI Data Length */
+#define DLEN_8			0x0000	/* Data Length = 8 Bits */
+#define DLEN_10			0x0800	/* Data Length = 10 Bits */
+#define DLEN_11			0x1000	/* Data Length = 11 Bits */
+#define DLEN_12			0x1800	/* Data Length = 12 Bits */
+#define DLEN_13			0x2000	/* Data Length = 13 Bits */
+#define DLEN_14			0x2800	/* Data Length = 14 Bits */
+#define DLEN_15			0x3000	/* Data Length = 15 Bits */
+#define DLEN_16			0x3800	/* Data Length = 16 Bits */
+#define POLC			0x4000	/* PPI Clock Polarity */
+#define POLS			0x8000	/* PPI Frame Sync Polarity */
+
+/* PPI_STATUS Masks */
+#define FLD			0x0400	/* Field Indicator */
+#define FT_ERR			0x0800	/* Frame Track Error */
+#define OVR			0x1000	/* FIFO Overflow Error */
+#define UNDR			0x2000	/* FIFO Underrun Error */
+#define ERR_DET			0x4000	/* Error Detected Indicator */
+#define ERR_NCOR		0x8000	/* Error Not Corrected Indicator */
+
+#endif
diff --git a/include/asm-blackfin/mach-common/bits/rtc.h b/include/asm-blackfin/mach-common/bits/rtc.h
new file mode 100644
index 0000000..f5a0cdb
--- /dev/null
+++ b/include/asm-blackfin/mach-common/bits/rtc.h
@@ -0,0 +1,42 @@
+/*
+ * RTC Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_RTC__
+#define __BFIN_PERIPHERAL_RTC__
+
+/* RTC_STAT and RTC_ALARM Masks */
+#define	RTC_SEC			0x0000003F	/* Real-Time Clock Seconds */
+#define	RTC_MIN			0x00000FC0	/* Real-Time Clock Minutes */
+#define	RTC_HR			0x0001F000	/* Real-Time Clock Hours */
+#define	RTC_DAY			0xFFFE0000	/* Real-Time Clock Days */
+
+#define RTC_SEC_P		0
+#define RTC_MIN_P		6
+#define RTC_HR_P		12
+#define RTC_DAY_P		17
+
+/*
+ * RTC_ALARM Macro
+ */
+#define SET_ALARM(day, hr, min, sec) \
+	( (((day) << RTC_DAY_P) & RTC_DAY) | \
+	  (((hr)  << RTC_HR_P ) & RTC_HR ) | \
+	  (((min) << RTC_MIN_P) & RTC_MIN) | \
+	  (((sec) << RTC_SEC_P) & RTC_SEC) )
+
+/* RTC_ICTL and RTC_ISTAT Masks */
+#define	STOPWATCH		0x0001	/* Stopwatch Interrupt Enable */
+#define	ALARM			0x0002	/* Alarm Interrupt Enable */
+#define	SECOND			0x0004	/* Seconds (1 Hz) Interrupt Enable */
+#define	MINUTE			0x0008	/* Minutes Interrupt Enable */
+#define	HOUR			0x0010	/* Hours Interrupt Enable */
+#define	DAY			0x0020	/* 24 Hours (Days) Interrupt Enable */
+#define	DAY_ALARM		0x0040	/* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
+#define	WRITE_PENDING		0x4000	/* Write Pending Status */
+#define	WRITE_COMPLETE		0x8000	/* Write Complete Interrupt Enable */
+
+/* RTC_FAST / RTC_PREN Mask */
+#define PREN			0x0001	/* Enable Prescaler, RTC Runs @1 Hz */
+
+#endif
diff --git a/include/asm-blackfin/mach-common/bits/spi.h b/include/asm-blackfin/mach-common/bits/spi.h
new file mode 100644
index 0000000..869dcb0
--- /dev/null
+++ b/include/asm-blackfin/mach-common/bits/spi.h
@@ -0,0 +1,67 @@
+/*
+ * SPI Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_SPI__
+#define __BFIN_PERIPHERAL_SPI__
+
+/* SPI_CTL Masks */
+#define	TIMOD			0x0003	/* Transfer Initiate Mode */
+#define RDBR_CORE		0x0000	/* RDBR Read Initiates, IRQ When RDBR Full */
+#define	TDBR_CORE		0x0001	/* TDBR Write Initiates, IRQ When TDBR Empty */
+#define RDBR_DMA		0x0002	/* DMA Read, DMA Until FIFO Empty */
+#define TDBR_DMA		0x0003	/* DMA Write, DMA Until FIFO Full */
+#define SZ			0x0004	/* Send Zero (When TDBR Empty, Send Zero/Last*) */
+#define GM			0x0008	/* Get More (When RDBR Full, Overwrite/Discard*) */
+#define PSSE			0x0010	/* Slave-Select Input Enable */
+#define EMISO			0x0020	/* Enable MISO As Output */
+#define SIZE			0x0100	/* Size of Words (16/8* Bits) */
+#define LSBF			0x0200	/* LSB First */
+#define CPHA			0x0400	/* Clock Phase */
+#define CPOL			0x0800	/* Clock Polarity */
+#define MSTR			0x1000	/* Master/Slave* */
+#define WOM			0x2000	/* Write Open Drain Master */
+#define SPE			0x4000	/* SPI Enable */
+
+/* SPI_FLG Masks */
+#define FLS1			0x0002	/* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLS2			0x0004	/* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLS3			0x0008	/* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLS4			0x0010	/* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLS5			0x0020	/* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLS6			0x0040	/* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLS7			0x0080	/* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
+#define FLG1			0x0200	/* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLG2			0x0400	/* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLG3			0x0800	/* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLG4			0x1000	/* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLG5			0x2000	/* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLG6			0x4000	/* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLG7			0x8000	/* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
+
+/* SPI_FLG Bit Positions */
+#define FLS1_P			0x0001	/* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLS2_P			0x0002	/* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLS3_P			0x0003	/* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLS4_P			0x0004	/* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLS5_P			0x0005	/* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLS6_P			0x0006	/* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLS7_P			0x0007	/* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
+#define FLG1_P			0x0009	/* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLG2_P			0x000A	/* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLG3_P			0x000B	/* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLG4_P			0x000C	/* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLG5_P			0x000D	/* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLG6_P			0x000E	/* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLG7_P			0x000F	/* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
+
+/* SPI_STAT Masks */
+#define SPIF			0x0001	/* SPI Finished (Single-Word Transfer Complete) */
+#define MODF			0x0002	/* Mode Fault Error (Another Device Tried To Become Master) */
+#define TXE			0x0004	/* Transmission Error (Data Sent With No New Data In TDBR) */
+#define TXS			0x0008	/* SPI_TDBR Data Buffer Status (Full/Empty*) */
+#define RBSY			0x0010	/* Receive Error (Data Received With RDBR Full) */
+#define RXS			0x0020	/* SPI_RDBR Data Buffer Status (Full/Empty*) */
+#define TXCOL			0x0040	/* Transmit Collision Error (Corrupt Data May Have Been Sent) */
+
+#endif
diff --git a/include/asm-blackfin/mach-common/bits/sport.h b/include/asm-blackfin/mach-common/bits/sport.h
new file mode 100644
index 0000000..88e7a5d
--- /dev/null
+++ b/include/asm-blackfin/mach-common/bits/sport.h
@@ -0,0 +1,89 @@
+/*
+ * SPORT Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_SPORT__
+#define __BFIN_PERIPHERAL_SPORT__
+
+/* SPORTx_TCR1 Masks */
+#define TSPEN			0x0001	/* TX enable */
+#define ITCLK			0x0002	/* Internal TX Clock Select */
+#define TDTYPE			0x000C	/* TX Data Formatting Select */
+#define DTYPE_NORM		0x0004	/* Data Format Normal */
+#define DTYPE_ULAW		0x0008	/* Compand Using u-Law */
+#define DTYPE_ALAW		0x000C	/* Compand Using A-Law */
+#define TLSBIT			0x0010	/* TX Bit Order */
+#define ITFS			0x0200	/* Internal TX Frame Sync Select */
+#define TFSR			0x0400	/* TX Frame Sync Required Select */
+#define DITFS			0x0800	/* Data Independent TX Frame Sync Select */
+#define LTFS			0x1000	/* Low TX Frame Sync Select */
+#define LATFS			0x2000	/* Late TX Frame Sync Select */
+#define TCKFE			0x4000	/* TX Clock Falling Edge Select */
+
+/* SPORTx_TCR2 Masks */
+#define SLEN			0x001F	/* TX Word Length */
+#define TXSE			0x0100	/* TX Secondary Enable */
+#define TSFSE			0x0200	/* TX Stereo Frame Sync Enable */
+#define TRFST			0x0400	/* TX Right-First Data Order */
+
+/* SPORTx_RCR1 Masks */
+#define RSPEN			0x0001	/* RX enable */
+#define IRCLK			0x0002	/* Internal RX Clock Select */
+#define RDTYPE			0x000C	/* RX Data Formatting Select */
+#define DTYPE_NORM		0x0004	/* Data Format Normal */
+#define DTYPE_ULAW		0x0008	/* Compand Using u-Law */
+#define DTYPE_ALAW		0x000C	/* Compand Using A-Law */
+#define RLSBIT			0x0010	/* RX Bit Order */
+#define IRFS			0x0200	/* Internal RX Frame Sync Select */
+#define RFSR			0x0400	/* RX Frame Sync Required Select */
+#define LRFS			0x1000	/* Low RX Frame Sync Select */
+#define LARFS			0x2000	/* Late RX Frame Sync Select */
+#define RCKFE			0x4000	/* RX Clock Falling Edge Select */
+
+/* SPORTx_RCR2 Masks */
+#define SLEN			0x001F	/* RX Word Length */
+#define RXSE			0x0100	/* RX Secondary Enable */
+#define RSFSE			0x0200	/* RX Stereo Frame Sync Enable */
+#define RRFST			0x0400	/* Right-First Data Order */
+
+/* SPORTx_STAT Masks */
+#define RXNE			0x0001	/* RX FIFO Not Empty Status */
+#define RUVF			0x0002	/* RX Underflow Status */
+#define ROVF			0x0004	/* RX Overflow Status */
+#define TXF			0x0008	/* TX FIFO Full Status */
+#define TUVF			0x0010	/* TX Underflow Status */
+#define TOVF			0x0020	/* TX Overflow Status */
+#define TXHRE			0x0040	/* TX Hold Register Empty */
+
+/* SPORTx_MCMC1 Masks */
+#define WSIZE			0xF000	/* Multichannel Window Size Field */
+#define WOFF			0x03FF	/* Multichannel Window Offset Field */
+
+/* SPORTx_MCMC2 Masks */
+#define MCCRM			0x0003	/* Multichannel Clock Recovery Mode */
+#define REC_BYPASS		0x0000	/* Bypass Mode (No Clock Recovery) */
+#define REC_2FROM4		0x0002	/* Recover 2 MHz Clock from 4 MHz Clock */
+#define REC_8FROM16		0x0003	/* Recover 8 MHz Clock from 16 MHz Clock */
+#define MCDTXPE			0x0004	/* Multichannel DMA Transmit Packing */
+#define MCDRXPE			0x0008	/* Multichannel DMA Receive Packing */
+#define MCMEN			0x0010	/* Multichannel Frame Mode Enable */
+#define FSDR			0x0080	/* Multichannel Frame Sync to Data Relationship */
+#define MFD			0xF000	/* Multichannel Frame Delay */
+#define MFD_0			0x0000	/* Multichannel Frame Delay = 0 */
+#define MFD_1			0x1000	/* Multichannel Frame Delay = 1 */
+#define MFD_2			0x2000	/* Multichannel Frame Delay = 2 */
+#define MFD_3			0x3000	/* Multichannel Frame Delay = 3 */
+#define MFD_4			0x4000	/* Multichannel Frame Delay = 4 */
+#define MFD_5			0x5000	/* Multichannel Frame Delay = 5 */
+#define MFD_6			0x6000	/* Multichannel Frame Delay = 6 */
+#define MFD_7			0x7000	/* Multichannel Frame Delay = 7 */
+#define MFD_8			0x8000	/* Multichannel Frame Delay = 8 */
+#define MFD_9			0x9000	/* Multichannel Frame Delay = 9 */
+#define MFD_10			0xA000	/* Multichannel Frame Delay = 10 */
+#define MFD_11			0xB000	/* Multichannel Frame Delay = 11 */
+#define MFD_12			0xC000	/* Multichannel Frame Delay = 12 */
+#define MFD_13			0xD000	/* Multichannel Frame Delay = 13 */
+#define MFD_14			0xE000	/* Multichannel Frame Delay = 14 */
+#define MFD_15			0xF000	/* Multichannel Frame Delay = 15 */
+
+#endif
diff --git a/include/asm-blackfin/mach-common/bits/timer.h b/include/asm-blackfin/mach-common/bits/timer.h
new file mode 100644
index 0000000..9513f80
--- /dev/null
+++ b/include/asm-blackfin/mach-common/bits/timer.h
@@ -0,0 +1,78 @@
+/*
+ * General Purpose Timer Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_TIMER__
+#define __BFIN_PERIPHERAL_TIMER__
+
+/* TIMER_ENABLE Masks */
+#define TIMEN0			0x0001		/* Enable Timer 0					*/
+#define TIMEN1			0x0002		/* Enable Timer 1					*/
+#define TIMEN2			0x0004		/* Enable Timer 2					*/
+#define TIMEN3			0x0008		/* Enable Timer 3					*/
+#define TIMEN4			0x0010		/* Enable Timer 4					*/
+#define TIMEN5			0x0020		/* Enable Timer 5					*/
+#define TIMEN6			0x0040		/* Enable Timer 6					*/
+#define TIMEN7			0x0080		/* Enable Timer 7					*/
+
+/* TIMER_DISABLE Masks */
+#define TIMDIS0			TIMEN0		/* Disable Timer 0					*/
+#define TIMDIS1			TIMEN1		/* Disable Timer 1					*/
+#define TIMDIS2			TIMEN2		/* Disable Timer 2					*/
+#define TIMDIS3			TIMEN3		/* Disable Timer 3					*/
+#define TIMDIS4			TIMEN4		/* Disable Timer 4					*/
+#define TIMDIS5			TIMEN5		/* Disable Timer 5					*/
+#define TIMDIS6			TIMEN6		/* Disable Timer 6					*/
+#define TIMDIS7			TIMEN7		/* Disable Timer 7					*/
+
+/* TIMER_STATUS Masks */
+#define TIMIL0			0x00000001	/* Timer 0 Interrupt				*/
+#define TIMIL1			0x00000002	/* Timer 1 Interrupt				*/
+#define TIMIL2			0x00000004	/* Timer 2 Interrupt				*/
+#define TIMIL3			0x00000008	/* Timer 3 Interrupt				*/
+#define TOVF_ERR0		0x00000010	/* Timer 0 Counter Overflow			*/
+#define TOVF_ERR1		0x00000020	/* Timer 1 Counter Overflow			*/
+#define TOVF_ERR2		0x00000040	/* Timer 2 Counter Overflow			*/
+#define TOVF_ERR3		0x00000080	/* Timer 3 Counter Overflow			*/
+#define TRUN0			0x00001000	/* Timer 0 Slave Enable Status		*/
+#define TRUN1			0x00002000	/* Timer 1 Slave Enable Status		*/
+#define TRUN2			0x00004000	/* Timer 2 Slave Enable Status		*/
+#define TRUN3			0x00008000	/* Timer 3 Slave Enable Status		*/
+#define TIMIL4			0x00010000	/* Timer 4 Interrupt				*/
+#define TIMIL5			0x00020000	/* Timer 5 Interrupt				*/
+#define TIMIL6			0x00040000	/* Timer 6 Interrupt				*/
+#define TIMIL7			0x00080000	/* Timer 7 Interrupt				*/
+#define TOVF_ERR4		0x00100000	/* Timer 4 Counter Overflow			*/
+#define TOVF_ERR5		0x00200000	/* Timer 5 Counter Overflow			*/
+#define TOVF_ERR6		0x00400000	/* Timer 6 Counter Overflow			*/
+#define TOVF_ERR7		0x00800000	/* Timer 7 Counter Overflow			*/
+#define TRUN4			0x10000000	/* Timer 4 Slave Enable Status		*/
+#define TRUN5			0x20000000	/* Timer 5 Slave Enable Status		*/
+#define TRUN6			0x40000000	/* Timer 6 Slave Enable Status		*/
+#define TRUN7			0x80000000	/* Timer 7 Slave Enable Status		*/
+
+/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
+#define TOVL_ERR0 TOVF_ERR0
+#define TOVL_ERR1 TOVF_ERR1
+#define TOVL_ERR2 TOVF_ERR2
+#define TOVL_ERR3 TOVF_ERR3
+#define TOVL_ERR4 TOVF_ERR4
+#define TOVL_ERR5 TOVF_ERR5
+#define TOVL_ERR6 TOVF_ERR6
+#define TOVL_ERR7 TOVF_ERR7
+
+/* TIMERx_CONFIG Masks */
+#define PWM_OUT			0x0001	/* Pulse-Width Modulation Output Mode	*/
+#define WDTH_CAP		0x0002	/* Width Capture Input Mode				*/
+#define EXT_CLK			0x0003	/* External Clock Mode					*/
+#define PULSE_HI		0x0004	/* Action Pulse (Positive/Negative*)	*/
+#define PERIOD_CNT		0x0008	/* Period Count							*/
+#define IRQ_ENA			0x0010	/* Interrupt Request Enable				*/
+#define TIN_SEL			0x0020	/* Timer Input Select					*/
+#define OUT_DIS			0x0040	/* Output Pad Disable					*/
+#define CLK_SEL			0x0080	/* Timer Clock Select					*/
+#define TOGGLE_HI		0x0100	/* PWM_OUT PULSE_HI Toggle Mode			*/
+#define EMU_RUN			0x0200	/* Emulation Behavior Select			*/
+#define ERR_TYP			0xC000	/* Error Type							*/
+
+#endif
diff --git a/include/asm-blackfin/mach-common/bits/trace.h b/include/asm-blackfin/mach-common/bits/trace.h
new file mode 100644
index 0000000..13e2134
--- /dev/null
+++ b/include/asm-blackfin/mach-common/bits/trace.h
@@ -0,0 +1,19 @@
+/*
+ * Trace Unit Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_TRACE__
+#define __BFIN_PERIPHERAL_TRACE__
+
+/* Trace Buffer Control (TBUFCTL) Register Masks */
+#define TBUFPWR       0x00000001
+#define TBUFEN        0x00000002
+#define TBUFOVF       0x00000004
+#define CMPLB_SINGLE  0x00000008
+#define CMPLP_DOUBLE  0x00000010
+#define CMPLB         (CMPLB_SINGLE | CMPLP_DOUBLE)
+
+/* Trace Buffer Status (TBUFSTAT) Register Masks */
+#define TBUFCNT       0x0000001F
+
+#endif
diff --git a/include/asm-blackfin/mach-common/bits/twi.h b/include/asm-blackfin/mach-common/bits/twi.h
new file mode 100644
index 0000000..8fa7d9f
--- /dev/null
+++ b/include/asm-blackfin/mach-common/bits/twi.h
@@ -0,0 +1,77 @@
+/*
+ * TWI Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_TWI__
+#define __BFIN_PERIPHERAL_TWI__
+
+/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
+#define	CLKLOW(x)		((x) & 0xFF)		/* Periods Clock Is Held Low */
+#define CLKHI(y)		(((y)&0xFF)<<0x8)	/* Periods Before New Clock Low */
+
+/* TWI_PRESCALE Masks */
+#define	PRESCALE		0x007F	/* SCLKs Per Internal Time Reference (10MHz) */
+#define	TWI_ENA			0x0080	/* TWI Enable */
+#define	SCCB			0x0200	/* SCCB Compatibility Enable */
+
+/* TWI_SLAVE_CTL Masks */
+#define	SEN			0x0001	/* Slave Enable */
+#define	SADD_LEN		0x0002	/* Slave Address Length */
+#define	STDVAL			0x0004	/* Slave Transmit Data Valid */
+#define	TSC_NAK			0x0008	/* NAK/ACK* Generated At Conclusion Of Transfer */
+#define	GEN			0x0010	/* General Call Adrress Matching Enabled */
+
+/* TWI_SLAVE_STAT Masks */
+#define	SDIR			0x0001	/* Slave Transfer Direction (Transmit/Receive*) */
+#define GCALL			0x0002	/* General Call Indicator */
+
+/* TWI_MASTER_CTRL Masks */
+#define	MEN			0x0001	/* Master Mode Enable */
+#define	MADD_LEN		0x0002	/* Master Address Length */
+#define	MDIR			0x0004	/* Master Transmit Direction (RX/TX*) */
+#define	FAST			0x0008	/* Use Fast Mode Timing Specs */
+#define	STOP			0x0010	/* Issue Stop Condition */
+#define	RSTART			0x0020	/* Repeat Start or Stop* At End Of Transfer */
+#define	DCNT			0x3FC0	/* Data Bytes To Transfer */
+#define	SDAOVR			0x4000	/* Serial Data Override */
+#define	SCLOVR			0x8000	/* Serial Clock Override */
+
+/* TWI_MASTER_STAT Masks */
+#define	MPROG			0x0001	/* Master Transfer In Progress */
+#define	LOSTARB			0x0002	/* Lost Arbitration Indicator (Xfer Aborted) */
+#define	ANAK			0x0004	/* Address Not Acknowledged */
+#define	DNAK			0x0008	/* Data Not Acknowledged */
+#define	BUFRDERR		0x0010	/* Buffer Read Error */
+#define	BUFWRERR		0x0020	/* Buffer Write Error */
+#define	SDASEN			0x0040	/* Serial Data Sense */
+#define	SCLSEN			0x0080	/* Serial Clock Sense */
+#define	BUSBUSY			0x0100	/* Bus Busy Indicator */
+
+/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
+#define	SINIT			0x0001	/* Slave Transfer Initiated */
+#define	SCOMP			0x0002	/* Slave Transfer Complete */
+#define	SERR			0x0004	/* Slave Transfer Error */
+#define	SOVF			0x0008	/* Slave Overflow */
+#define	MCOMP			0x0010	/* Master Transfer Complete */
+#define	MERR			0x0020	/* Master Transfer Error */
+#define	XMTSERV			0x0040	/* Transmit FIFO Service */
+#define	RCVSERV			0x0080	/* Receive FIFO Service */
+
+/* TWI_FIFO_CTRL Masks */
+#define	XMTFLUSH		0x0001	/* Transmit Buffer Flush */
+#define	RCVFLUSH		0x0002	/* Receive Buffer Flush */
+#define	XMTINTLEN		0x0004	/* Transmit Buffer Interrupt Length */
+#define	RCVINTLEN		0x0008	/* Receive Buffer Interrupt Length */
+
+/* TWI_FIFO_STAT Masks */
+#define	XMTSTAT			0x0003	/* Transmit FIFO Status */
+#define	XMT_EMPTY		0x0000	/* Transmit FIFO Empty */
+#define	XMT_HALF		0x0001	/* Transmit FIFO Has 1 Byte To Write */
+#define	XMT_FULL		0x0003	/* Transmit FIFO Full (2 Bytes To Write) */
+
+#define	RCVSTAT			0x000C	/* Receive FIFO Status */
+#define	RCV_EMPTY		0x0000	/* Receive FIFO Empty */
+#define	RCV_HALF		0x0004	/* Receive FIFO Has 1 Byte To Read */
+#define	RCV_FULL		0x000C	/* Receive FIFO Full (2 Bytes To Read) */
+
+#endif
diff --git a/include/asm-blackfin/mach-common/bits/uart.h b/include/asm-blackfin/mach-common/bits/uart.h
new file mode 100644
index 0000000..ac1ba11
--- /dev/null
+++ b/include/asm-blackfin/mach-common/bits/uart.h
@@ -0,0 +1,98 @@
+/*
+ * UART Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_UART__
+#define __BFIN_PERIPHERAL_UART__
+
+/* UARTx_LCR Masks */
+#define WLS			0x03	/* Word Length Select */
+#define WLS_5			0x00	/* 5 bit word */
+#define WLS_6			0x01	/* 6 bit word */
+#define WLS_7			0x02	/* 7 bit word */
+#define WLS_8			0x03	/* 8 bit word */
+#define STB			0x04	/* Stop Bits */
+#define PEN			0x08	/* Parity Enable */
+#define EPS			0x10	/* Even Parity Select */
+#define STP			0x20	/* Stick Parity */
+#define SB			0x40	/* Set Break */
+#define DLAB			0x80	/* Divisor Latch Access */
+
+#define DLAB_P			0x07
+#define SB_P			0x06
+#define STP_P			0x05
+#define EPS_P			0x04
+#define PEN_P			0x03
+#define STB_P			0x02
+#define WLS_P1			0x01
+#define WLS_P0			0x00
+
+/* UARTx_MCR Mask */
+#define XOFF			0x01	/* Transmitter off */
+#define MRTS			0x02	/* Manual Request to Send */
+#define RFIT			0x04	/* Receive FIFO IRQ Threshold */
+#define RFRT			0x08	/* Receive FIFO RTS Threshold */
+#define LOOP_ENA		0x10	/* Loopback Mode Enable */
+#define FCPOL			0x20	/* Flow Control Pin Polarity */
+#define ARTS			0x40	/* Auto RTS generation for RX handshake */
+#define ACTS			0x80	/* Auto CTS operation for TX handshake */
+
+#define XOFF_P			0
+#define MRTS_P			1
+#define RFIT_P			2
+#define RFRT_P			3
+#define LOOP_ENA_P		4
+#define FCPOL_P			5
+#define ARTS_P			6
+#define ACTS_P			7
+
+/* UARTx_LSR Masks */
+#define DR			0x01	/* Data Ready */
+#define OE			0x02	/* Overrun Error */
+#define PE			0x04	/* Parity Error */
+#define FE			0x08	/* Framing Error */
+#define BI			0x10	/* Break Interrupt */
+#define THRE			0x20	/* THR Empty */
+#define TEMT			0x40	/* TSR and UART_THR Empty */
+
+#define DR_P			0x00
+#define OE_P			0x01
+#define PE_P			0x02
+#define FE_P			0x03
+#define BI_P			0x04
+#define THRE_P			0x05
+#define TEMT_P			0x06
+
+/* UARTx_IER Masks */
+#define ERBFI			0x01	/* Enable Receive Buffer Full Interrupt */
+#define ETBEI			0x02	/* Enable Transmit Buffer Empty Interrupt */
+#define ELSI			0x04	/* Enable RX Status Interrupt */
+
+#define ERBFI_P			0x00
+#define ETBEI_P			0x01
+#define ELSI_P			0x02
+
+/* UARTx_IIR Masks */
+#define NINT			0x01	/* Pending Interrupt */
+#define STATUS			0x06	/* Highest Priority Pending Interrupt */
+
+#define NINT_P			0x00
+#define STATUS_P0		0x01
+#define STATUS_P1		0x02
+
+/* UARTx_GCTL Masks */
+#define UCEN			0x01	/* Enable UARTx Clocks */
+#define IREN			0x02	/* Enable IrDA Mode */
+#define TPOLC			0x04	/* IrDA TX Polarity Change */
+#define RPOLC			0x08	/* IrDA RX Polarity Change */
+#define FPE			0x10	/* Force Parity Error On Transmit */
+#define FFE			0x20	/* Force Framing Error On Transmit */
+
+#define UCEN_P			0x00
+#define IREN_P			0x01
+#define TPOLC_P			0x02
+#define RPOLC_P			0x03
+#define FPE_P			0x04
+#define FFE_P			0x05
+
+#endif
diff --git a/include/asm-blackfin/mach-common/bits/watchdog.h b/include/asm-blackfin/mach-common/bits/watchdog.h
new file mode 100644
index 0000000..75924f9
--- /dev/null
+++ b/include/asm-blackfin/mach-common/bits/watchdog.h
@@ -0,0 +1,19 @@
+/*
+ * Watchdog Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_WATCHDOG__
+#define __BFIN_PERIPHERAL_WATCHDOG__
+
+/* Watchdog Timer WDOG_CTL Register Masks */
+
+#define WDEV			0x0006	/* event generated on roll over */
+#define WDEV_RESET		0x0000	/* generate reset event on roll over */
+#define WDEV_NMI		0x0002	/* generate NMI event on roll over */
+#define WDEV_GPI		0x0004	/* generate GP IRQ on roll over */
+#define WDEV_NONE		0x0006	/* no event on roll over */
+#define WDEN			0x0FF0	/* enable watchdog */
+#define WDDIS			0x0AD0	/* disable watchdog */
+#define WDRO			0x8000	/* watchdog rolled over latch */
+
+#endif